arch/m68k/coldfire/pit.c
Source file repositories/reference/linux-study-clean/arch/m68k/coldfire/pit.c
File Facts
- System
- Linux kernel
- Corpus path
arch/m68k/coldfire/pit.c- Extension
.c- Size
- 4295 bytes
- Lines
- 163
- Domain
- Architecture Layer
- Bucket
- arch/m68k
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/sched.hlinux/param.hlinux/init.hlinux/interrupt.hlinux/irq.hlinux/clockchips.hasm/machdep.hasm/io.hasm/coldfire.hasm/mcfpit.hasm/mcfsim.h
Detected Declarations
function cf_pit_set_periodicfunction cf_pit_set_oneshotfunction cf_pit_shutdownfunction cf_pit_next_eventfunction pit_tickfunction pit_read_clkfunction hw_timer_init
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/***************************************************************************/
/*
* pit.c -- Freescale ColdFire PIT timer. Currently this type of
* hardware timer only exists in the Freescale ColdFire
* 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
* family members will probably use it too.
*
* Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
*/
/***************************************************************************/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/param.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <asm/machdep.h>
#include <asm/io.h>
#include <asm/coldfire.h>
#include <asm/mcfpit.h>
#include <asm/mcfsim.h>
/***************************************************************************/
/*
* By default use timer1 as the system clock timer.
*/
#define FREQ ((MCF_CLK / 2) / 64)
#define TA(a) (MCFPIT_BASE1 + (a))
#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
static u32 pit_cnt;
/*
* Initialize the PIT timer.
*
* This is also called after resume to bring the PIT into operation again.
*/
static int cf_pit_set_periodic(struct clock_event_device *evt)
{
mcf_write16(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
mcf_write16(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
mcf_write16(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
return 0;
}
static int cf_pit_set_oneshot(struct clock_event_device *evt)
{
mcf_write16(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
mcf_write16(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
return 0;
}
static int cf_pit_shutdown(struct clock_event_device *evt)
{
mcf_write16(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
return 0;
}
/*
* Program the next event in oneshot mode
*
* Delta is given in PIT ticks
*/
static int cf_pit_next_event(unsigned long delta,
struct clock_event_device *evt)
{
mcf_write16(delta, TA(MCFPIT_PMR));
return 0;
}
struct clock_event_device cf_pit_clockevent = {
.name = "pit",
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_state_shutdown = cf_pit_shutdown,
.set_state_periodic = cf_pit_set_periodic,
.set_state_oneshot = cf_pit_set_oneshot,
.set_next_event = cf_pit_next_event,
.shift = 32,
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/sched.h`, `linux/param.h`, `linux/init.h`, `linux/interrupt.h`, `linux/irq.h`, `linux/clockchips.h`, `asm/machdep.h`.
- Detected declarations: `function cf_pit_set_periodic`, `function cf_pit_set_oneshot`, `function cf_pit_shutdown`, `function cf_pit_next_event`, `function pit_tick`, `function pit_read_clk`, `function hw_timer_init`.
- Atlas domain: Architecture Layer / arch/m68k.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.