arch/m68k/include/asm/m520xsim.h

Source file repositories/reference/linux-study-clean/arch/m68k/include/asm/m520xsim.h

File Facts

System
Linux kernel
Corpus path
arch/m68k/include/asm/m520xsim.h
Extension
.h
Size
7323 bytes
Lines
214
Domain
Architecture Layer
Bucket
arch/m68k
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef m520xsim_h
#define m520xsim_h
/****************************************************************************/

#define	CPU_NAME		"COLDFIRE(m520x)"
#define	CPU_INSTR_PER_JIFFY	3
#define	MCF_BUSCLK		(MCF_CLK / 2)

#include <asm/m52xxacr.h>

/*
 *  Define the 520x SIM register set addresses.
 */
#define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
#define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
#define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
#define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
#define MCFINTC_SIMR        0x1c        /* Set interrupt mask 0-63 */
#define MCFINTC_CIMR        0x1d        /* Clear interrupt mask 0-63 */
#define MCFINTC_ICR0        0x40        /* Base ICR register */

/*
 *  The common interrupt controller code just wants to know the absolute
 *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
 *  The 520x family only has a single INTC unit.
 */
#define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)
#define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)
#define	MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)
#define MCFINTC1_SIMR       (0)
#define MCFINTC1_CIMR       (0)
#define	MCFINTC1_ICR0       (0)
#define MCFINTC2_SIMR       (0)
#define MCFINTC2_CIMR       (0)
#define MCFINTC2_ICR0       (0)

#define MCFINT_VECBASE      64
#define MCFINT_UART0        26          /* Interrupt number for UART0 */
#define MCFINT_UART1        27          /* Interrupt number for UART1 */
#define MCFINT_UART2        28          /* Interrupt number for UART2 */
#define MCFINT_I2C0         30          /* Interrupt number for I2C */
#define MCFINT_QSPI         31          /* Interrupt number for QSPI */
#define MCFINT_FECRX0	    36		/* Interrupt number for FEC RX */
#define MCFINT_FECTX0	    40		/* Interrupt number for FEC RX */
#define MCFINT_FECENTC0	    42		/* Interrupt number for FEC RX */
#define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */

#define MCF_IRQ_UART0	    (MCFINT_VECBASE + MCFINT_UART0)
#define MCF_IRQ_UART1	    (MCFINT_VECBASE + MCFINT_UART1)
#define MCF_IRQ_UART2	    (MCFINT_VECBASE + MCFINT_UART2)

#define MCF_IRQ_FECRX0	    (MCFINT_VECBASE + MCFINT_FECRX0)
#define MCF_IRQ_FECTX0	    (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)

#define	MCF_IRQ_QSPI	    (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1        (MCFINT_VECBASE + MCFINT_PIT1)

#define MCF_IRQ_I2C0        (MCFINT_VECBASE + MCFINT_I2C0)
/*
 *  SDRAM configuration registers.
 */
#define MCFSIM_SDMR         0xFC0a8000	/* SDRAM Mode/Extended Mode Register */
#define MCFSIM_SDCR         0xFC0a8004	/* SDRAM Control Register */
#define MCFSIM_SDCFG1       0xFC0a8008	/* SDRAM Configuration Register 1 */
#define MCFSIM_SDCFG2       0xFC0a800c	/* SDRAM Configuration Register 2 */
#define MCFSIM_SDCS0        0xFC0a8110	/* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1        0xFC0a8114	/* SDRAM Chip Select 1 Configuration */

/*
 * EPORT and GPIO registers.
 */
#define MCFEPORT_EPPAR			0xFC088000
#define MCFEPORT_EPDDR			0xFC088002
#define MCFEPORT_EPIER			0xFC088003
#define MCFEPORT_EPDR			0xFC088004
#define MCFEPORT_EPPDR			0xFC088005
#define MCFEPORT_EPFR			0xFC088006

#define MCFGPIO_PODR_BUSCTL		0xFC0A4000
#define MCFGPIO_PODR_BE			0xFC0A4001
#define MCFGPIO_PODR_CS			0xFC0A4002
#define MCFGPIO_PODR_FECI2C		0xFC0A4003
#define MCFGPIO_PODR_QSPI		0xFC0A4004
#define MCFGPIO_PODR_TIMER		0xFC0A4005
#define MCFGPIO_PODR_UART		0xFC0A4006
#define MCFGPIO_PODR_FECH		0xFC0A4007

Annotation

Implementation Notes