arch/m68k/include/asm/m5441xsim.h

Source file repositories/reference/linux-study-clean/arch/m68k/include/asm/m5441xsim.h

File Facts

System
Linux kernel
Corpus path
arch/m68k/include/asm/m5441xsim.h
Extension
.h
Size
11549 bytes
Lines
379
Domain
Architecture Layer
Bucket
arch/m68k
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef m5441xsim_h
#define m5441xsim_h

#include <linux/bits.h>

#define CPU_NAME		"COLDFIRE(m5441x)"
#define CPU_INSTR_PER_JIFFY	2
#define MCF_BUSCLK		(MCF_CLK / 2)
#define MACHINE			MACH_M5441X
#define FPUTYPE			0
#define IOMEMBASE		0xe0000000
#define IOMEMSIZE		0x20000000

#include <asm/m54xxacr.h>

/*
 *  Reset Controller Module.
 */

#define	MCF_RCR			0xec090000
#define	MCF_RSR			0xec090001

#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */

/*
 *  Interrupt Controller Modules.
 */
/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
#define MCFINT_VECBASE		64
#define MCFINT0_VECBASE		MCFINT_VECBASE
#define MCFINT1_VECBASE		(MCFINT0_VECBASE + 64)
#define MCFINT2_VECBASE		(MCFINT1_VECBASE + 64)

/* interrupt controller 0 */
#define MCFINTC0_SIMR		0xfc04801c
#define MCFINTC0_CIMR		0xfc04801d
#define	MCFINTC0_ICR0		0xfc048040
/* interrupt controller 1 */
#define MCFINTC1_SIMR		0xfc04c01c
#define MCFINTC1_CIMR		0xfc04c01d
#define	MCFINTC1_ICR0		0xfc04c040
/* interrupt controller 2 */
#define MCFINTC2_SIMR		0xfc05001c
#define MCFINTC2_CIMR		0xfc05001d
#define	MCFINTC2_ICR0		0xfc050040

/* on interrupt controller 0 */
#define MCFINT0_EPORT0		1
#define MCFINT0_UART0		26
#define MCFINT0_UART1		27
#define MCFINT0_UART2		28
#define MCFINT0_UART3		29
#define MCFINT0_I2C0		30
#define MCFINT0_DSPI0		31

#define MCFINT0_TIMER0		32
#define MCFINT0_TIMER1		33
#define MCFINT0_TIMER2		34
#define MCFINT0_TIMER3		35

#define MCFINT0_FECRX0		36
#define MCFINT0_FECTX0		40
#define MCFINT0_FECENTC0	42

#define MCFINT0_FECRX1		49
#define MCFINT0_FECTX1		53
#define MCFINT0_FECENTC1	55

/* on interrupt controller 1 */
#define MCFINT1_FLEXCAN0_IFL	0
#define MCFINT1_FLEXCAN0_BOFF	1
#define MCFINT1_FLEXCAN0_ERR	3
#define MCFINT1_FLEXCAN1_IFL	4
#define MCFINT1_FLEXCAN1_BOFF	5
#define MCFINT1_FLEXCAN1_ERR	7
#define MCFINT1_UART4		48
#define MCFINT1_UART5		49
#define MCFINT1_UART6		50
#define MCFINT1_UART7		51
#define MCFINT1_UART8		52
#define MCFINT1_UART9		53
#define MCFINT1_DSPI1		54
#define MCFINT1_DSPI2		55
#define MCFINT1_DSPI3		56
#define MCFINT1_I2C1		57
#define MCFINT1_I2C2		58
#define MCFINT1_I2C3		59
#define MCFINT1_I2C4		60
#define MCFINT1_I2C5		61

Annotation

Implementation Notes