arch/m68k/include/asm/pgtable_mm.h
Source file repositories/reference/linux-study-clean/arch/m68k/include/asm/pgtable_mm.h
File Facts
- System
- Linux kernel
- Corpus path
arch/m68k/include/asm/pgtable_mm.h- Extension
.h- Size
- 4701 bytes
- Lines
- 169
- Domain
- Architecture Layer
- Bucket
- arch/m68k
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm-generic/pgtable-nopmd.hasm-generic/pgtable-nopud.hasm/setup.hasm/processor.hlinux/sched.hlinux/threads.hasm/virtconvert.hasm/sun3_pgtable.hasm/mcf_pgtable.hasm/motorola_pgtable.h
Detected Declarations
function update_mmu_cache_range
Annotated Snippet
#ifndef _M68K_PGTABLE_H
#define _M68K_PGTABLE_H
#if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE)
#include <asm-generic/pgtable-nopmd.h>
#else
#include <asm-generic/pgtable-nopud.h>
#endif
#include <asm/setup.h>
#ifndef __ASSEMBLER__
#include <asm/processor.h>
#include <linux/sched.h>
#include <linux/threads.h>
/*
* This file contains the functions and defines necessary to modify and use
* the m68k page table tree.
*/
#include <asm/virtconvert.h>
/* Certain architectures need to do special things when pte's
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
#define set_pte(pteptr, pteval) \
do{ \
*(pteptr) = (pteval); \
} while(0)
/* PMD_SHIFT determines the size of the area a second-level page table can map */
#if CONFIG_PGTABLE_LEVELS == 3
#define PMD_SHIFT 18
#endif
#define PMD_SIZE (1UL << PMD_SHIFT)
#define PMD_MASK (~(PMD_SIZE-1))
/* PGDIR_SHIFT determines what a third-level page table entry can map */
#ifdef CONFIG_SUN3
#define PGDIR_SHIFT 17
#elif defined(CONFIG_COLDFIRE)
#define PGDIR_SHIFT 22
#else
#define PGDIR_SHIFT 25
#endif
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
/*
* entries per page directory level: the m68k is configured as three-level,
* so we do have PMD level physically.
*/
#ifdef CONFIG_SUN3
#define PTRS_PER_PTE 16
#define __PAGETABLE_PMD_FOLDED 1
#define PTRS_PER_PMD 1
#define PTRS_PER_PGD 2048
#elif defined(CONFIG_COLDFIRE)
#define PTRS_PER_PTE 512
#define __PAGETABLE_PMD_FOLDED 1
#define PTRS_PER_PMD 1
#define PTRS_PER_PGD 1024
#else
#define PTRS_PER_PTE 64
#define PTRS_PER_PMD 128
#define PTRS_PER_PGD 128
#endif
#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
/* Virtual address region for use by kernel_map() */
#ifdef CONFIG_SUN3
#define KMAP_START 0x0dc00000
#define KMAP_END 0x0e000000
#elif defined(CONFIG_COLDFIRE)
#define KMAP_START 0xe0000000
#define KMAP_END 0xf0000000
#elif defined(CONFIG_VIRT)
#define KMAP_START 0xdf000000
#define KMAP_END 0xff000000
#else
#define KMAP_START 0xd0000000
#define KMAP_END 0xf0000000
#endif
#ifdef CONFIG_SUN3
extern unsigned long m68k_vmalloc_end;
#define VMALLOC_START 0x0f800000
Annotation
- Immediate include surface: `asm-generic/pgtable-nopmd.h`, `asm-generic/pgtable-nopud.h`, `asm/setup.h`, `asm/processor.h`, `linux/sched.h`, `linux/threads.h`, `asm/virtconvert.h`, `asm/sun3_pgtable.h`.
- Detected declarations: `function update_mmu_cache_range`.
- Atlas domain: Architecture Layer / arch/m68k.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.