arch/m68k/include/asm/tlbflush.h
Source file repositories/reference/linux-study-clean/arch/m68k/include/asm/tlbflush.h
File Facts
- System
- Linux kernel
- Corpus path
arch/m68k/include/asm/tlbflush.h- Extension
.h- Size
- 5853 bytes
- Lines
- 274
- Domain
- Architecture Layer
- Bucket
- arch/m68k
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/current.hasm/mcfmmu.h
Detected Declarations
function flush_tlb_kernel_pagefunction __flush_tlbfunction __flush_tlb040_onefunction __flush_tlb_onefunction entriesfunction flush_tlb_mmfunction flush_tlb_pagefunction flush_tlb_rangefunction flush_tlb_kernel_rangefunction flush_tlb_allfunction flush_tlb_mmfunction flush_tlb_pagefunction flush_tlb_rangefunction flush_tlb_kernel_rangefunction flush_tlb_kernel_pagefunction __flush_tlbfunction __flush_tlb_onefunction entriesfunction flush_tlb_mmfunction flush_tlb_pagefunction flush_tlb_rangefunction flush_tlb_kernel_page
Annotated Snippet
if (pmeg_alloc[addr] == 1) {
pmeg_alloc[addr] = 0;
pmeg_ctx[addr] = 0;
pmeg_vaddr[addr] = 0;
}
}
}
/* Clear user TLB entries within the context named in mm */
static inline void flush_tlb_mm (struct mm_struct *mm)
{
unsigned char oldctx;
unsigned char seg;
unsigned long i;
oldctx = sun3_get_context();
sun3_put_context(mm->context);
for (i = 0; i < TASK_SIZE; i += SUN3_PMEG_SIZE) {
seg = sun3_get_segmap(i);
if (seg == SUN3_INVALID_PMEG)
continue;
sun3_put_segmap(i, SUN3_INVALID_PMEG);
pmeg_alloc[seg] = 0;
pmeg_ctx[seg] = 0;
pmeg_vaddr[seg] = 0;
}
sun3_put_context(oldctx);
}
/* Flush a single TLB page. In this case, we're limited to flushing a
single PMEG */
static inline void flush_tlb_page (struct vm_area_struct *vma,
unsigned long addr)
{
unsigned char oldctx;
unsigned char i;
oldctx = sun3_get_context();
sun3_put_context(vma->vm_mm->context);
addr &= ~SUN3_PMEG_MASK;
if((i = sun3_get_segmap(addr)) != SUN3_INVALID_PMEG)
{
pmeg_alloc[i] = 0;
pmeg_ctx[i] = 0;
pmeg_vaddr[i] = 0;
sun3_put_segmap (addr, SUN3_INVALID_PMEG);
}
sun3_put_context(oldctx);
}
/* Flush a range of pages from TLB. */
static inline void flush_tlb_range (struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
struct mm_struct *mm = vma->vm_mm;
unsigned char seg, oldctx;
start &= ~SUN3_PMEG_MASK;
oldctx = sun3_get_context();
sun3_put_context(mm->context);
while(start < end)
{
if((seg = sun3_get_segmap(start)) == SUN3_INVALID_PMEG)
goto next;
if(pmeg_ctx[seg] == mm->context) {
pmeg_alloc[seg] = 0;
pmeg_ctx[seg] = 0;
pmeg_vaddr[seg] = 0;
}
sun3_put_segmap(start, SUN3_INVALID_PMEG);
next:
start += SUN3_PMEG_SIZE;
}
sun3_put_context(oldctx);
}
static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
flush_tlb_all();
}
/* Flush kernel page from TLB. */
static inline void flush_tlb_kernel_page (unsigned long addr)
{
Annotation
- Immediate include surface: `asm/current.h`, `asm/mcfmmu.h`.
- Detected declarations: `function flush_tlb_kernel_page`, `function __flush_tlb`, `function __flush_tlb040_one`, `function __flush_tlb_one`, `function entries`, `function flush_tlb_mm`, `function flush_tlb_page`, `function flush_tlb_range`, `function flush_tlb_kernel_range`, `function flush_tlb_all`.
- Atlas domain: Architecture Layer / arch/m68k.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.