arch/microblaze/boot/dts/system.dts

Source file repositories/reference/linux-study-clean/arch/microblaze/boot/dts/system.dts

File Facts

System
Linux kernel
Corpus path
arch/microblaze/boot/dts/system.dts
Extension
.dts
Size
10017 bytes
Lines
354
Domain
Architecture Layer
Bucket
arch/microblaze
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Device Tree Generator version: 1.1
 *
 * (C) Copyright 2007-2008 Xilinx, Inc.
 * (C) Copyright 2007-2009 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * CAUTION: This file is automatically generated by libgen.
 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
 *
 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
 */

/dts-v1/;
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "xlnx,microblaze";
	model = "testing";
	DDR2_SDRAM: memory@90000000 {
		device_type = "memory";
		reg = < 0x90000000 0x10000000 >;
	} ;
	aliases {
		ethernet0 = &Hard_Ethernet_MAC;
		serial0 = &RS232_Uart_1;
	} ;
	chosen {
		bootargs = "console=ttyUL0,115200 highres=on";
		stdout-path = "/plb@0/serial@84000000";
	} ;
	cpus {
		#address-cells = <1>;
		#cpus = <0x1>;
		#size-cells = <0>;
		microblaze_0: cpu@0 {
			clock-frequency = <125000000>;
			compatible = "xlnx,microblaze-7.10.d";
			d-cache-baseaddr = <0x90000000>;
			d-cache-highaddr = <0x9fffffff>;
			d-cache-line-size = <0x10>;
			d-cache-size = <0x2000>;
			device_type = "cpu";
			i-cache-baseaddr = <0x90000000>;
			i-cache-highaddr = <0x9fffffff>;
			i-cache-line-size = <0x10>;
			i-cache-size = <0x2000>;
			model = "microblaze,7.10.d";
			reg = <0>;
			timebase-frequency = <125000000>;
			xlnx,addr-tag-bits = <0xf>;
			xlnx,allow-dcache-wr = <0x1>;
			xlnx,allow-icache-wr = <0x1>;
			xlnx,area-optimized = <0x0>;
			xlnx,cache-byte-size = <0x2000>;
			xlnx,d-lmb = <0x1>;
			xlnx,d-opb = <0x0>;
			xlnx,d-plb = <0x1>;
			xlnx,data-size = <0x20>;
			xlnx,dcache-addr-tag = <0xf>;
			xlnx,dcache-always-used = <0x1>;
			xlnx,dcache-byte-size = <0x2000>;
			xlnx,dcache-line-len = <0x4>;
			xlnx,dcache-use-fsl = <0x1>;
			xlnx,debug-enabled = <0x1>;
			xlnx,div-zero-exception = <0x1>;
			xlnx,dopb-bus-exception = <0x0>;
			xlnx,dynamic-bus-sizing = <0x1>;

Annotation

Implementation Notes