arch/microblaze/include/asm/pvr.h

Source file repositories/reference/linux-study-clean/arch/microblaze/include/asm/pvr.h

File Facts

System
Linux kernel
Corpus path
arch/microblaze/include/asm/pvr.h
Extension
.h
Size
8791 bytes
Lines
225
Domain
Architecture Layer
Bucket
arch/microblaze
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pvr_s {
	unsigned pvr[12];
};

/* The following taken from Xilinx's standalone BSP pvr.h */

/* Basic PVR mask */
#define PVR0_PVR_FULL_MASK		0x80000000
#define PVR0_USE_BARREL_MASK		0x40000000
#define PVR0_USE_DIV_MASK		0x20000000
#define PVR0_USE_HW_MUL_MASK		0x10000000
#define PVR0_USE_FPU_MASK		0x08000000
#define PVR0_USE_EXC_MASK		0x04000000
#define PVR0_USE_ICACHE_MASK		0x02000000
#define PVR0_USE_DCACHE_MASK		0x01000000
#define PVR0_USE_MMU			0x00800000
#define PVR0_USE_BTC			0x00400000
#define PVR0_ENDI			0x00200000
#define PVR0_VERSION_MASK		0x0000FF00
#define PVR0_USER1_MASK			0x000000FF

/* User 2 PVR mask */
#define PVR1_USER2_MASK			0xFFFFFFFF

/* Configuration PVR masks */
#define PVR2_D_OPB_MASK			0x80000000 /* or AXI */
#define PVR2_D_LMB_MASK			0x40000000
#define PVR2_I_OPB_MASK			0x20000000 /* or AXI */
#define PVR2_I_LMB_MASK			0x10000000
#define PVR2_INTERRUPT_IS_EDGE_MASK	0x08000000
#define PVR2_EDGE_IS_POSITIVE_MASK	0x04000000
#define PVR2_D_PLB_MASK			0x02000000 /* new */
#define PVR2_I_PLB_MASK			0x01000000 /* new */
#define PVR2_INTERCONNECT		0x00800000 /* new */
#define PVR2_USE_EXTEND_FSL		0x00080000 /* new */
#define PVR2_USE_FSL_EXC		0x00040000 /* new */
#define PVR2_USE_MSR_INSTR		0x00020000
#define PVR2_USE_PCMP_INSTR		0x00010000
#define PVR2_AREA_OPTIMISED		0x00008000
#define PVR2_USE_BARREL_MASK		0x00004000
#define PVR2_USE_DIV_MASK		0x00002000
#define PVR2_USE_HW_MUL_MASK		0x00001000
#define PVR2_USE_FPU_MASK		0x00000800
#define PVR2_USE_MUL64_MASK		0x00000400
#define PVR2_USE_FPU2_MASK		0x00000200 /* new */
#define PVR2_USE_IPLBEXC 		0x00000100
#define PVR2_USE_DPLBEXC		0x00000080
#define PVR2_OPCODE_0x0_ILL_MASK	0x00000040
#define PVR2_UNALIGNED_EXC_MASK		0x00000020
#define PVR2_ILL_OPCODE_EXC_MASK	0x00000010
#define PVR2_IOPB_BUS_EXC_MASK		0x00000008 /* or AXI */
#define PVR2_DOPB_BUS_EXC_MASK		0x00000004 /* or AXI */
#define PVR2_DIV_ZERO_EXC_MASK		0x00000002
#define PVR2_FPU_EXC_MASK		0x00000001

/* Debug and exception PVR masks */
#define PVR3_DEBUG_ENABLED_MASK		0x80000000
#define PVR3_NUMBER_OF_PC_BRK_MASK	0x1E000000
#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK	0x00380000
#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK	0x0000E000
#define PVR3_FSL_LINKS_MASK		0x00000380

/* ICache config PVR masks */
#define PVR4_USE_ICACHE_MASK		0x80000000 /* ICU */
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK	0x7C000000 /* ICTS */
#define PVR4_ICACHE_ALLOW_WR_MASK	0x01000000 /* ICW */
#define PVR4_ICACHE_LINE_LEN_MASK	0x00E00000 /* ICLL */
#define PVR4_ICACHE_BYTE_SIZE_MASK	0x001F0000 /* ICBS */
#define PVR4_ICACHE_ALWAYS_USED		0x00008000 /* IAU */
#define PVR4_ICACHE_INTERFACE		0x00002000 /* ICI */

/* DCache config PVR masks */
#define PVR5_USE_DCACHE_MASK		0x80000000 /* DCU */
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK	0x7C000000 /* DCTS */
#define PVR5_DCACHE_ALLOW_WR_MASK	0x01000000 /* DCW */
#define PVR5_DCACHE_LINE_LEN_MASK	0x00E00000 /* DCLL */
#define PVR5_DCACHE_BYTE_SIZE_MASK	0x001F0000 /* DCBS */
#define PVR5_DCACHE_ALWAYS_USED		0x00008000 /* DAU */
#define PVR5_DCACHE_USE_WRITEBACK	0x00004000 /* DWB */
#define PVR5_DCACHE_INTERFACE		0x00002000 /* DCI */

/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK	0xFFFFFFFF

/* ICache high address PVR mask */
#define PVR7_ICACHE_HIGHADDR_MASK	0xFFFFFFFF

/* DCache base address PVR mask */
#define PVR8_DCACHE_BASEADDR_MASK	0xFFFFFFFF

Annotation

Implementation Notes