arch/microblaze/kernel/cpu/cache.c
Source file repositories/reference/linux-study-clean/arch/microblaze/kernel/cpu/cache.c
File Facts
- System
- Linux kernel
- Corpus path
arch/microblaze/kernel/cpu/cache.c- Extension
.c- Size
- 16973 bytes
- Lines
- 657
- Domain
- Architecture Layer
- Bucket
- arch/microblaze
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/cacheflush.hlinux/cache.hasm/cpuinfo.hasm/pvr.h
Detected Declarations
function Copyrightfunction __disable_icache_msrfunction __enable_dcache_msrfunction __disable_dcache_msrfunction __enable_icache_nomsrfunction __disable_icache_nomsrfunction __enable_dcache_nomsrfunction __disable_dcache_nomsrfunction __flush_icache_range_msr_irqfunction __flush_icache_range_nomsr_irqfunction __flush_icache_range_noirqfunction __flush_icache_all_msr_irqfunction __flush_icache_all_nomsr_irqfunction __flush_icache_all_noirqfunction __invalidate_dcache_all_msr_irqfunction __invalidate_dcache_all_nomsr_irqfunction __invalidate_dcache_all_noirq_wtfunction __invalidate_dcache_all_wbfunction __invalidate_dcache_range_wbfunction __invalidate_dcache_range_nomsr_wtfunction __invalidate_dcache_range_msr_irq_wtfunction __invalidate_dcache_range_nomsr_irqfunction __flush_dcache_all_wbfunction __flush_dcache_range_wbfunction microblaze_cache_init
Annotated Snippet
if (cpuinfo.dcache_wb) {
pr_info("wb_msr\n");
mbc = (struct scache *)&wb_msr;
if (cpuinfo.ver_code <= CPUVER_7_20_D) {
/* MS: problem with signal handling - hw bug */
pr_info("WB won't work properly\n");
}
} else {
if (cpuinfo.ver_code >= CPUVER_7_20_A) {
pr_info("wt_msr_noirq\n");
mbc = (struct scache *)&wt_msr_noirq;
} else {
pr_info("wt_msr\n");
mbc = (struct scache *)&wt_msr;
}
}
} else {
if (cpuinfo.dcache_wb) {
pr_info("wb_nomsr\n");
mbc = (struct scache *)&wb_nomsr;
if (cpuinfo.ver_code <= CPUVER_7_20_D) {
/* MS: problem with signal handling - hw bug */
pr_info("WB won't work properly\n");
}
} else {
if (cpuinfo.ver_code >= CPUVER_7_20_A) {
pr_info("wt_nomsr_noirq\n");
mbc = (struct scache *)&wt_nomsr_noirq;
} else {
pr_info("wt_nomsr\n");
mbc = (struct scache *)&wt_nomsr;
}
}
}
/*
* FIXME Invalidation is done in U-BOOT
* WT cache: Data is already written to main memory
* WB cache: Discard data on noMMU which caused that kernel doesn't boot
*/
/* invalidate_dcache(); */
enable_dcache();
invalidate_icache();
enable_icache();
}
Annotation
- Immediate include surface: `asm/cacheflush.h`, `linux/cache.h`, `asm/cpuinfo.h`, `asm/pvr.h`.
- Detected declarations: `function Copyright`, `function __disable_icache_msr`, `function __enable_dcache_msr`, `function __disable_dcache_msr`, `function __enable_icache_nomsr`, `function __disable_icache_nomsr`, `function __enable_dcache_nomsr`, `function __disable_dcache_nomsr`, `function __flush_icache_range_msr_irq`, `function __flush_icache_range_nomsr_irq`.
- Atlas domain: Architecture Layer / arch/microblaze.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.