arch/microblaze/kernel/cpu/cpuinfo.c
Source file repositories/reference/linux-study-clean/arch/microblaze/kernel/cpu/cpuinfo.c
File Facts
- System
- Linux kernel
- Corpus path
arch/microblaze/kernel/cpu/cpuinfo.c- Extension
.c- Size
- 3261 bytes
- Lines
- 143
- Domain
- Architecture Layer
- Bucket
- arch/microblaze
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/init.hasm/cpuinfo.hasm/pvr.h
Detected Declarations
function setup_cpuinfofunction setup_cpuinfo_clk
Annotated Snippet
#include <linux/clk.h>
#include <linux/init.h>
#include <asm/cpuinfo.h>
#include <asm/pvr.h>
const struct cpu_ver_key cpu_ver_lookup[] = {
/* These key value are as per MBV field in PVR0 */
{"5.00.a", 0x01},
{"5.00.b", 0x02},
{"5.00.c", 0x03},
{"6.00.a", 0x04},
{"6.00.b", 0x06},
{"7.00.a", 0x05},
{"7.00.b", 0x07},
{"7.10.a", 0x08},
{"7.10.b", 0x09},
{"7.10.c", 0x0a},
{"7.10.d", 0x0b},
{"7.20.a", 0x0c},
{"7.20.b", 0x0d},
{"7.20.c", 0x0e},
{"7.20.d", 0x0f},
{"7.30.a", 0x10},
{"7.30.b", 0x11},
{"8.00.a", 0x12},
{"8.00.b", 0x13},
{"8.10.a", 0x14},
{"8.20.a", 0x15},
{"8.20.b", 0x16},
{"8.30.a", 0x17},
{"8.40.a", 0x18},
{"8.40.b", 0x19},
{"8.50.a", 0x1a},
{"8.50.b", 0x1c},
{"8.50.c", 0x1e},
{"9.0", 0x1b},
{"9.1", 0x1d},
{"9.2", 0x1f},
{"9.3", 0x20},
{"9.4", 0x21},
{"9.5", 0x22},
{"9.6", 0x23},
{"10.0", 0x24},
{"11.0", 0x25},
{NULL, 0},
};
/*
* FIXME Not sure if the actual key is defined by Xilinx in the PVR
*/
const struct family_string_key family_string_lookup[] = {
{"virtex2", 0x4},
{"virtex2pro", 0x5},
{"spartan3", 0x6},
{"virtex4", 0x7},
{"virtex5", 0x8},
{"spartan3e", 0x9},
{"spartan3a", 0xa},
{"spartan3an", 0xb},
{"spartan3adsp", 0xc},
{"spartan6", 0xd},
{"virtex6", 0xe},
{"virtex7", 0xf},
/* FIXME There is no key code defined for spartan2 */
{"spartan2", 0xf0},
{"kintex7", 0x10},
{"artix7", 0x11},
{"zynq7000", 0x12},
{"UltraScale Virtex", 0x13},
{"UltraScale Kintex", 0x14},
{"UltraScale+ Zynq", 0x15},
{"UltraScale+ Virtex", 0x16},
{"UltraScale+ Kintex", 0x17},
{"Spartan7", 0x18},
{NULL, 0},
};
struct cpuinfo cpuinfo;
static struct device_node *cpu;
void __init setup_cpuinfo(void)
{
cpu = of_get_cpu_node(0, NULL);
if (!cpu)
pr_err("You don't have cpu or are missing cpu reg property!!!\n");
pr_info("%s: initialising\n", __func__);
switch (cpu_has_pvr()) {
case 0:
Annotation
- Immediate include surface: `linux/clk.h`, `linux/init.h`, `asm/cpuinfo.h`, `asm/pvr.h`.
- Detected declarations: `function setup_cpuinfo`, `function setup_cpuinfo_clk`.
- Atlas domain: Architecture Layer / arch/microblaze.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.