arch/microblaze/lib/libgcc.h

File Facts

System

Linux kernel

Corpus path

arch/microblaze/lib/libgcc.h

Extension

.h

Size

763 bytes

Lines

34

Domain

Architecture Layer

Bucket

arch/microblaze

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• asm/byteorder.h

Detected Declarations

• struct DWstruct
• struct DWstruct

Annotated Snippet

struct DWstruct {
	int high, low;
};
#elif defined(__LITTLE_ENDIAN)
struct DWstruct {
	int low, high;
};
#else
#error I feel sick.
#endif

typedef union {
	struct DWstruct s;
	long long ll;
} DWunion;

extern long long __ashldi3(long long u, word_type b);
extern long long __ashrdi3(long long u, word_type b);
extern word_type __cmpdi2(long long a, long long b);
extern long long __lshrdi3(long long u, word_type b);
extern long long __muldi3(long long u, long long v);
extern word_type __ucmpdi2(unsigned long long a, unsigned long long b);

#endif /* __ASM_LIBGCC_H */

Annotation

• Immediate include surface: `asm/byteorder.h`.
• Detected declarations: `struct DWstruct`, `struct DWstruct`.
• Atlas domain: Architecture Layer / arch/microblaze.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.