arch/mips/alchemy/common/setup.c

Source file repositories/reference/linux-study-clean/arch/mips/alchemy/common/setup.c

File Facts

System
Linux kernel
Corpus path
arch/mips/alchemy/common/setup.c
Extension
.c
Size
3423 bytes
Lines
106
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/mm.h>
#include <linux/dma-map-ops.h> /* for dma_default_coherent */

#include <asm/bootinfo.h>
#include <asm/mipsregs.h>

#include <au1000.h>

static bool alchemy_dma_coherent(void)
{
	switch (alchemy_get_cputype()) {
	case ALCHEMY_CPU_AU1000:
	case ALCHEMY_CPU_AU1500:
	case ALCHEMY_CPU_AU1100:
		return false;
	case ALCHEMY_CPU_AU1200:
		/* Au1200 AB USB does not support coherent memory */
		if ((read_c0_prid() & PRID_REV_MASK) == 0)
			return false;
		return true;
	default:
		return true;
	}
}

void __init plat_mem_setup(void)
{
	alchemy_set_lpj();

	if (au1xxx_cpu_needs_config_od())
		/* Various early Au1xx0 errata corrected by this */
		set_c0_config(1 << 19); /* Set Config[OD] */
	else
		/* Clear to obtain best system bus performance */
		clear_c0_config(1 << 19); /* Clear Config[OD] */

	dma_default_coherent = alchemy_dma_coherent();

	board_setup();	/* board specific setup */

	/* IO/MEM resources. */
	set_io_port_base(0);
	ioport_resource.start = IOPORT_RESOURCE_START;
	ioport_resource.end = IOPORT_RESOURCE_END;
	iomem_resource.start = IOMEM_RESOURCE_START;
	iomem_resource.end = IOMEM_RESOURCE_END;
}

#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
/* This routine should be valid for all Au1x based boards */
phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
	unsigned long start = ALCHEMY_PCI_MEMWIN_START;
	unsigned long end = ALCHEMY_PCI_MEMWIN_END;

	/* Don't fixup 36-bit addresses */
	if ((phys_addr >> 32) != 0)
		return phys_addr;

	/* Check for PCI memory window */
	if (phys_addr >= start && (phys_addr + size - 1) <= end)
		return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);

	/* default nop */
	return phys_addr;
}

unsigned long io_remap_pfn_range_pfn(unsigned long pfn, unsigned long size)
{
	phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);

	return phys_addr >> PAGE_SHIFT;
}
EXPORT_SYMBOL(io_remap_pfn_range_pfn);

#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */

Annotation

Implementation Notes