arch/mips/ath25/ar2315_regs.h

Source file repositories/reference/linux-study-clean/arch/mips/ath25/ar2315_regs.h

File Facts

System
Linux kernel
Corpus path
arch/mips/ath25/ar2315_regs.h
Extension
.h
Size
15552 bytes
Lines
411
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
#define __ASM_MACH_ATH25_AR2315_REGS_H

/*
 * IRQs
 */
#define AR2315_IRQ_MISC		(MIPS_CPU_IRQ_BASE + 2)	/* C0_CAUSE: 0x0400 */
#define AR2315_IRQ_WLAN0	(MIPS_CPU_IRQ_BASE + 3)	/* C0_CAUSE: 0x0800 */
#define AR2315_IRQ_ENET0	(MIPS_CPU_IRQ_BASE + 4)	/* C0_CAUSE: 0x1000 */
#define AR2315_IRQ_LCBUS_PCI	(MIPS_CPU_IRQ_BASE + 5)	/* C0_CAUSE: 0x2000 */
#define AR2315_IRQ_WLAN0_POLL	(MIPS_CPU_IRQ_BASE + 6)	/* C0_CAUSE: 0x4000 */

/*
 * Miscellaneous interrupts, which share IP2.
 */
#define AR2315_MISC_IRQ_UART0		0
#define AR2315_MISC_IRQ_I2C_RSVD	1
#define AR2315_MISC_IRQ_SPI		2
#define AR2315_MISC_IRQ_AHB		3
#define AR2315_MISC_IRQ_APB		4
#define AR2315_MISC_IRQ_TIMER		5
#define AR2315_MISC_IRQ_GPIO		6
#define AR2315_MISC_IRQ_WATCHDOG	7
#define AR2315_MISC_IRQ_IR_RSVD		8
#define AR2315_MISC_IRQ_COUNT		9

/*
 * Address map
 */
#define AR2315_SPI_READ_BASE	0x08000000	/* SPI flash */
#define AR2315_SPI_READ_SIZE	0x01000000
#define AR2315_WLAN0_BASE	0x10000000	/* Wireless MMR */
#define AR2315_PCI_BASE		0x10100000	/* PCI MMR */
#define AR2315_PCI_SIZE		0x00001000
#define AR2315_SDRAMCTL_BASE	0x10300000	/* SDRAM MMR */
#define AR2315_SDRAMCTL_SIZE	0x00000020
#define AR2315_LOCAL_BASE	0x10400000	/* Local bus MMR */
#define AR2315_ENET0_BASE	0x10500000	/* Ethernet MMR */
#define AR2315_RST_BASE		0x11000000	/* Reset control MMR */
#define AR2315_RST_SIZE		0x00000100
#define AR2315_UART0_BASE	0x11100000	/* UART MMR */
#define AR2315_SPI_MMR_BASE	0x11300000	/* SPI flash MMR */
#define AR2315_SPI_MMR_SIZE	0x00000010
#define AR2315_PCI_EXT_BASE	0x80000000	/* PCI external */
#define AR2315_PCI_EXT_SIZE	0x40000000

/*
 * Configuration registers
 */

/* Cold reset register */
#define AR2315_COLD_RESET		0x0000

#define AR2315_RESET_COLD_AHB		0x00000001
#define AR2315_RESET_COLD_APB		0x00000002
#define AR2315_RESET_COLD_CPU		0x00000004
#define AR2315_RESET_COLD_CPUWARM	0x00000008
#define AR2315_RESET_SYSTEM		(RESET_COLD_CPU |\
					 RESET_COLD_APB |\
					 RESET_COLD_AHB)  /* full system */
#define AR2317_RESET_SYSTEM		0x00000010

/* Reset register */
#define AR2315_RESET			0x0004

#define AR2315_RESET_WARM_WLAN0_MAC	0x00000001  /* warm reset WLAN0 MAC */
#define AR2315_RESET_WARM_WLAN0_BB	0x00000002  /* warm reset WLAN0 BB */
#define AR2315_RESET_MPEGTS_RSVD	0x00000004  /* warm reset MPEG-TS */
#define AR2315_RESET_PCIDMA		0x00000008  /* warm reset PCI ahb/dma */
#define AR2315_RESET_MEMCTL		0x00000010  /* warm reset mem control */
#define AR2315_RESET_LOCAL		0x00000020  /* warm reset local bus */
#define AR2315_RESET_I2C_RSVD		0x00000040  /* warm reset I2C bus */
#define AR2315_RESET_SPI		0x00000080  /* warm reset SPI iface */
#define AR2315_RESET_UART0		0x00000100  /* warm reset UART0 */
#define AR2315_RESET_IR_RSVD		0x00000200  /* warm reset IR iface */
#define AR2315_RESET_EPHY0		0x00000400  /* cold reset ENET0 phy */
#define AR2315_RESET_ENET0		0x00000800  /* cold reset ENET0 MAC */

/* AHB master arbitration control */
#define AR2315_AHB_ARB_CTL		0x0008

#define AR2315_ARB_CPU			0x00000001  /* CPU, default */
#define AR2315_ARB_WLAN			0x00000002  /* WLAN */
#define AR2315_ARB_MPEGTS_RSVD		0x00000004  /* MPEG-TS */
#define AR2315_ARB_LOCAL		0x00000008  /* Local bus */
#define AR2315_ARB_PCI			0x00000010  /* PCI bus */
#define AR2315_ARB_ETHERNET		0x00000020  /* Ethernet */
#define AR2315_ARB_RETRY		0x00000100  /* Retry policy (debug) */

/* Config Register */

Annotation

Implementation Notes