arch/mips/ath25/ar5312_regs.h

Source file repositories/reference/linux-study-clean/arch/mips/ath25/ar5312_regs.h

File Facts

System
Linux kernel
Corpus path
arch/mips/ath25/ar5312_regs.h
Extension
.h
Size
9146 bytes
Lines
225
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
#define __ASM_MACH_ATH25_AR5312_REGS_H

/*
 * IRQs
 */
#define AR5312_IRQ_WLAN0	(MIPS_CPU_IRQ_BASE + 2)	/* C0_CAUSE: 0x0400 */
#define AR5312_IRQ_ENET0	(MIPS_CPU_IRQ_BASE + 3)	/* C0_CAUSE: 0x0800 */
#define AR5312_IRQ_ENET1	(MIPS_CPU_IRQ_BASE + 4)	/* C0_CAUSE: 0x1000 */
#define AR5312_IRQ_WLAN1	(MIPS_CPU_IRQ_BASE + 5)	/* C0_CAUSE: 0x2000 */
#define AR5312_IRQ_MISC		(MIPS_CPU_IRQ_BASE + 6)	/* C0_CAUSE: 0x4000 */

/*
 * Miscellaneous interrupts, which share IP6.
 */
#define AR5312_MISC_IRQ_TIMER		0
#define AR5312_MISC_IRQ_AHB_PROC	1
#define AR5312_MISC_IRQ_AHB_DMA		2
#define AR5312_MISC_IRQ_GPIO		3
#define AR5312_MISC_IRQ_UART0		4
#define AR5312_MISC_IRQ_UART0_DMA	5
#define AR5312_MISC_IRQ_WATCHDOG	6
#define AR5312_MISC_IRQ_LOCAL		7
#define AR5312_MISC_IRQ_SPI		8
#define AR5312_MISC_IRQ_COUNT		9

/*
 * Address Map
 *
 * The AR5312 supports 2 enet MACS, even though many reference boards only
 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
 * PHY or PHY switch. The AR2312 supports 1 enet MAC.
 */
#define AR5312_WLAN0_BASE		0x18000000
#define AR5312_ENET0_BASE		0x18100000
#define AR5312_ENET1_BASE		0x18200000
#define AR5312_SDRAMCTL_BASE		0x18300000
#define AR5312_SDRAMCTL_SIZE		0x00000010
#define AR5312_FLASHCTL_BASE		0x18400000
#define AR5312_FLASHCTL_SIZE		0x00000010
#define AR5312_WLAN1_BASE		0x18500000
#define AR5312_UART0_BASE		0x1c000000	/* UART MMR */
#define AR5312_GPIO_BASE		0x1c002000
#define AR5312_GPIO_SIZE		0x00000010
#define AR5312_RST_BASE			0x1c003000
#define AR5312_RST_SIZE			0x00000100
#define AR5312_FLASH_BASE		0x1e000000
#define AR5312_FLASH_SIZE		0x00800000

/*
 * Need these defines to determine true number of ethernet MACs
 */
#define AR5312_AR5312_REV2	0x0052		/* AR5312 WMAC (AP31) */
#define AR5312_AR5312_REV7	0x0057		/* AR5312 WMAC (AP30-040) */
#define AR5312_AR2313_REV8	0x0058		/* AR2313 WMAC (AP43-030) */

/* Reset/Timer Block Address Map */
#define AR5312_TIMER		0x0000 /* countdown timer */
#define AR5312_RELOAD		0x0004 /* timer reload value */
#define AR5312_WDT_CTRL		0x0008 /* watchdog cntrl */
#define AR5312_WDT_TIMER	0x000c /* watchdog timer */
#define AR5312_ISR		0x0010 /* Intr Status Reg */
#define AR5312_IMR		0x0014 /* Intr Mask Reg */
#define AR5312_RESET		0x0020
#define AR5312_CLOCKCTL1	0x0064
#define AR5312_SCRATCH		0x006c
#define AR5312_PROCADDR		0x0070
#define AR5312_PROC1		0x0074
#define AR5312_DMAADDR		0x0078
#define AR5312_DMA1		0x007c
#define AR5312_ENABLE		0x0080 /* interface enb */
#define AR5312_REV		0x0090 /* revision */

/* AR5312_WDT_CTRL register bit field definitions */
#define AR5312_WDT_CTRL_IGNORE	0x00000000	/* ignore expiration */
#define AR5312_WDT_CTRL_NMI	0x00000001
#define AR5312_WDT_CTRL_RESET	0x00000002

/* AR5312_ISR register bit field definitions */
#define AR5312_ISR_TIMER	0x00000001
#define AR5312_ISR_AHBPROC	0x00000002
#define AR5312_ISR_AHBDMA	0x00000004
#define AR5312_ISR_GPIO		0x00000008
#define AR5312_ISR_UART0	0x00000010
#define AR5312_ISR_UART0DMA	0x00000020
#define AR5312_ISR_WD		0x00000040
#define AR5312_ISR_LOCAL	0x00000080

/* AR5312_RESET register bit field definitions */
#define AR5312_RESET_SYSTEM		0x00000001  /* cold reset full system */

Annotation

Implementation Notes