arch/mips/bcm63xx/reset.c

Source file repositories/reference/linux-study-clean/arch/mips/bcm63xx/reset.c

File Facts

System: Linux kernel
Corpus path: arch/mips/bcm63xx/reset.c
Extension: .c
Size: 7000 bytes
Lines: 220
Domain: Architecture Layer
Bucket: arch/mips
Inferred role: Architecture Layer: exported/initcall integration point
Status: integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.

Dependency Surface

linux/init.h
linux/export.h
linux/mutex.h
linux/err.h
linux/clk.h
linux/delay.h
bcm63xx_cpu.h
bcm63xx_io.h
bcm63xx_regs.h
bcm63xx_reset.h

Detected Declarations

function bcm63xx_reset_bits_init
function __bcm63xx_core_set_reset
function bcm63xx_core_set_reset
export bcm63xx_core_set_reset

Annotated Snippet

#include <linux/init.h>
#include <linux/export.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_io.h>
#include <bcm63xx_regs.h>
#include <bcm63xx_reset.h>

#define __GEN_RESET_BITS_TABLE(__cpu)					\
	[BCM63XX_RESET_SPI]		= BCM## __cpu ##_RESET_SPI,	\
	[BCM63XX_RESET_ENET]		= BCM## __cpu ##_RESET_ENET,	\
	[BCM63XX_RESET_USBH]		= BCM## __cpu ##_RESET_USBH,	\
	[BCM63XX_RESET_USBD]		= BCM## __cpu ##_RESET_USBD,	\
	[BCM63XX_RESET_DSL]		= BCM## __cpu ##_RESET_DSL,	\
	[BCM63XX_RESET_SAR]		= BCM## __cpu ##_RESET_SAR,	\
	[BCM63XX_RESET_EPHY]		= BCM## __cpu ##_RESET_EPHY,	\
	[BCM63XX_RESET_ENETSW]		= BCM## __cpu ##_RESET_ENETSW,	\
	[BCM63XX_RESET_PCM]		= BCM## __cpu ##_RESET_PCM,	\
	[BCM63XX_RESET_MPI]		= BCM## __cpu ##_RESET_MPI,	\
	[BCM63XX_RESET_PCIE]		= BCM## __cpu ##_RESET_PCIE,	\
	[BCM63XX_RESET_PCIE_EXT]	= BCM## __cpu ##_RESET_PCIE_EXT,

#define BCM3368_RESET_SPI	SOFTRESET_3368_SPI_MASK
#define BCM3368_RESET_ENET	SOFTRESET_3368_ENET_MASK
#define BCM3368_RESET_USBH	0
#define BCM3368_RESET_USBD	SOFTRESET_3368_USBS_MASK
#define BCM3368_RESET_DSL	0
#define BCM3368_RESET_SAR	0
#define BCM3368_RESET_EPHY	SOFTRESET_3368_EPHY_MASK
#define BCM3368_RESET_ENETSW	0
#define BCM3368_RESET_PCM	SOFTRESET_3368_PCM_MASK
#define BCM3368_RESET_MPI	SOFTRESET_3368_MPI_MASK
#define BCM3368_RESET_PCIE	0
#define BCM3368_RESET_PCIE_EXT	0

#define BCM6328_RESET_SPI	SOFTRESET_6328_SPI_MASK
#define BCM6328_RESET_ENET	0
#define BCM6328_RESET_USBH	SOFTRESET_6328_USBH_MASK
#define BCM6328_RESET_USBD	SOFTRESET_6328_USBS_MASK
#define BCM6328_RESET_DSL	0
#define BCM6328_RESET_SAR	SOFTRESET_6328_SAR_MASK
#define BCM6328_RESET_EPHY	SOFTRESET_6328_EPHY_MASK
#define BCM6328_RESET_ENETSW	SOFTRESET_6328_ENETSW_MASK
#define BCM6328_RESET_PCM	SOFTRESET_6328_PCM_MASK
#define BCM6328_RESET_MPI	0
#define BCM6328_RESET_PCIE	\
				(SOFTRESET_6328_PCIE_MASK |		\
				 SOFTRESET_6328_PCIE_CORE_MASK |	\
				 SOFTRESET_6328_PCIE_HARD_MASK)
#define BCM6328_RESET_PCIE_EXT	SOFTRESET_6328_PCIE_EXT_MASK

#define BCM6338_RESET_SPI	SOFTRESET_6338_SPI_MASK
#define BCM6338_RESET_ENET	SOFTRESET_6338_ENET_MASK
#define BCM6338_RESET_USBH	SOFTRESET_6338_USBH_MASK
#define BCM6338_RESET_USBD	SOFTRESET_6338_USBS_MASK
#define BCM6338_RESET_DSL	SOFTRESET_6338_ADSL_MASK
#define BCM6338_RESET_SAR	SOFTRESET_6338_SAR_MASK
#define BCM6338_RESET_EPHY	0
#define BCM6338_RESET_ENETSW	0
#define BCM6338_RESET_PCM	0
#define BCM6338_RESET_MPI	0
#define BCM6338_RESET_PCIE	0
#define BCM6338_RESET_PCIE_EXT	0

#define BCM6348_RESET_SPI	SOFTRESET_6348_SPI_MASK
#define BCM6348_RESET_ENET	SOFTRESET_6348_ENET_MASK
#define BCM6348_RESET_USBH	SOFTRESET_6348_USBH_MASK
#define BCM6348_RESET_USBD	SOFTRESET_6348_USBS_MASK
#define BCM6348_RESET_DSL	SOFTRESET_6348_ADSL_MASK
#define BCM6348_RESET_SAR	SOFTRESET_6348_SAR_MASK
#define BCM6348_RESET_EPHY	0
#define BCM6348_RESET_ENETSW	0
#define BCM6348_RESET_PCM	0
#define BCM6348_RESET_MPI	0
#define BCM6348_RESET_PCIE	0
#define BCM6348_RESET_PCIE_EXT	0

#define BCM6358_RESET_SPI	SOFTRESET_6358_SPI_MASK
#define BCM6358_RESET_ENET	SOFTRESET_6358_ENET_MASK
#define BCM6358_RESET_USBH	SOFTRESET_6358_USBH_MASK
#define BCM6358_RESET_USBD	0
#define BCM6358_RESET_DSL	SOFTRESET_6358_ADSL_MASK
#define BCM6358_RESET_SAR	SOFTRESET_6358_SAR_MASK
#define BCM6358_RESET_EPHY	SOFTRESET_6358_EPHY_MASK
#define BCM6358_RESET_ENETSW	0
#define BCM6358_RESET_PCM	SOFTRESET_6358_PCM_MASK
#define BCM6358_RESET_MPI	SOFTRESET_6358_MPI_MASK

Annotation

Immediate include surface: `linux/init.h`, `linux/export.h`, `linux/mutex.h`, `linux/err.h`, `linux/clk.h`, `linux/delay.h`, `bcm63xx_cpu.h`, `bcm63xx_io.h`.
Detected declarations: `function bcm63xx_reset_bits_init`, `function __bcm63xx_core_set_reset`, `function bcm63xx_core_set_reset`, `export bcm63xx_core_set_reset`.
Atlas domain: Architecture Layer / arch/mips.
Implementation status: integration implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.