arch/mips/boot/compressed/ld.script

File Facts

System

Linux kernel

Corpus path

arch/mips/boot/compressed/ld.script

Extension

.script

Size

928 bytes

Lines

61

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: arch/mips

Status

atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

OUTPUT_ARCH(mips)
ENTRY(start)
PHDRS {
	text PT_LOAD FLAGS(7); /* RWX */
}
SECTIONS
{
	/* Text and read-only data */
	/* . = VMLINUZ_LOAD_ADDRESS; */
	.text : {
		*(.text)
		*(.rodata)
	}: text
	/* End of text section */

	/* Writable data */
	.data : {
		*(.data)
		/* Put the compressed image here */
		__image_begin = .;
		*(.image)
		__image_end = .;
		CONSTRUCTORS
		. = ALIGN(16);
	}

	.appended_dtb : {
		__appended_dtb = .;
		/* leave space for appended DTB */
		. += 0x100000;
	}

	_edata = .;
	/* End of data section */

	/* BSS */
	.bss : {
		*(.bss)
	}
	. = ALIGN(16);
	_end = .;

	/* Sections to be discarded */
	/DISCARD/ : {
		*(.MIPS.options)
		*(.options)
		*(.pdr)
		*(.reginfo)
		*(.comment)
		*(.note)
	}
}

Annotation

• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.