arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts- Extension
.dts- Size
- 629 bytes
- Lines
- 38
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/gpio/gpio.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device tree source for D-Link DSR-500N.
*
* Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
*/
/include/ "dlink_dsr-500n-1000n.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "dlink,dsr-500n";
compatible = "dlink,dsr-500n", "cavium,octeon-3860";
soc@0 {
uart0: serial@1180000000800 {
clock-frequency = <300000000>;
};
};
leds {
compatible = "gpio-leds";
led-usb {
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
};
led-wps {
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
led-wireless {
label = "2.4g";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
};
};
};
Annotation
- Immediate include surface: `dt-bindings/gpio/gpio.h`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.