arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi

Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi

File Facts

System
Linux kernel
Corpus path
arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi
Extension
.dtsi
Size
5945 bytes
Lines
233
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/* OCTEON 3XXX DTS common parts. */

/dts-v1/;

/ {
	compatible = "cavium,octeon-3860";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&ciu>;

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges; /* Direct mapping */

		ciu: interrupt-controller@1070000000000 {
			compatible = "cavium,octeon-3860-ciu";
			interrupt-controller;
			/* Interrupts are specified by two parts:
			 * 1) Controller register (0 or 1)
			 * 2) Bit within the register (0..63)
			 */
			#interrupt-cells = <2>;
			reg = <0x10700 0x00000000 0x0 0x7000>;
		};

		gpio: gpio-controller@1070000000800 {
			#gpio-cells = <2>;
			compatible = "cavium,octeon-3860-gpio";
			reg = <0x10700 0x00000800 0x0 0x100>;
			gpio-controller;
			/* Interrupts are specified by two parts:
			 * 1) GPIO pin number (0..15)
			 * 2) Triggering (1 - edge rising
			 *		  2 - edge falling
			 *		  4 - level active high
			 *		  8 - level active low)
			 */
			interrupt-controller;
			#interrupt-cells = <2>;
			/* The GPIO pin connect to 16 consecutive CUI bits */
			interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
				     <0 20>, <0 21>, <0 22>, <0 23>,
				     <0 24>, <0 25>, <0 26>, <0 27>,
				     <0 28>, <0 29>, <0 30>, <0 31>;
		};

		smi0: mdio@1180000001800 {
			compatible = "cavium,octeon-3860-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x11800 0x00001800 0x0 0x40>;
		};

		pip: pip@11800a0000000 {
			compatible = "cavium,octeon-3860-pip";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x11800 0xa0000000 0x0 0x2000>;

			interface@0 {
				compatible = "cavium,octeon-3860-pip-interface";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>; /* interface */

				ethernet@0 {
					compatible = "cavium,octeon-3860-pip-port";

Annotation

Implementation Notes