arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts

Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts

File Facts

System
Linux kernel
Corpus path
arch/mips/boot/dts/cavium-octeon/octeon_68xx.dts
Extension
.dts
Size
16058 bytes
Lines
627
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/*
 * OCTEON 68XX device tree skeleton.
 *
 * This device tree is pruned and patched by early boot code before
 * use.	 Because of this, it contains a super-set of the available
 * devices and properties.
 */
/ {
	compatible = "cavium,octeon-6880";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&ciu2>;

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges; /* Direct mapping */

		ciu2: interrupt-controller@1070100000000 {
			compatible = "cavium,octeon-6880-ciu2";
			interrupt-controller;
			/* Interrupts are specified by two parts:
			 * 1) Controller register (0 or 7)
			 * 2) Bit within the register (0..63)
			 */
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x10701 0x00000000 0x0 0x4000000>;
		};

		gpio: gpio-controller@1070000000800 {
			#gpio-cells = <2>;
			compatible = "cavium,octeon-3860-gpio";
			reg = <0x10700 0x00000800 0x0 0x100>;
			gpio-controller;
			/* Interrupts are specified by two parts:
			 * 1) GPIO pin number (0..15)
			 * 2) Triggering (1 - edge rising
			 *		  2 - edge falling
			 *		  4 - level active high
			 *		  8 - level active low)
			 */
			interrupt-controller;
			#interrupt-cells = <2>;
			/* The GPIO pins connect to 16 consecutive CUI bits */
			interrupts = <7 0>,  <7 1>,  <7 2>,  <7 3>,
				     <7 4>,  <7 5>,  <7 6>,  <7 7>,
				     <7 8>,  <7 9>,  <7 10>, <7 11>,
				     <7 12>, <7 13>, <7 14>, <7 15>;
		};

		smi0: mdio@1180000003800 {
			compatible = "cavium,octeon-3860-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x11800 0x00003800 0x0 0x40>;

			phy0: ethernet-phy@6 {
				compatible = "marvell,88e1118";
				marvell,reg-init =
					/* Fix rx and tx clock transition timing */
					<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
					/* Adjust LED drive. */
					<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
					/* irq, blink-activity, blink-link */
					<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
				reg = <6>;

Annotation

Implementation Notes