arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/boot/dts/loongson/loongson64c_4core_rs780e.dts- Extension
.dts- Size
- 518 bytes
- Lines
- 26
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
loongson64c-package.dtsirs780e-pch.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "loongson64c-package.dtsi"
#include "rs780e-pch.dtsi"
/ {
compatible = "loongson,loongson64c-4core-rs780e";
};
&package0 {
htpic: interrupt-controller@efdfb000080 {
compatible = "loongson,htpic-1.0";
reg = <0xefd 0xfb000080 0x40>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&liointc>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
<25 IRQ_TYPE_LEVEL_HIGH>,
<26 IRQ_TYPE_LEVEL_HIGH>,
<27 IRQ_TYPE_LEVEL_HIGH>;
};
};
Annotation
- Immediate include surface: `loongson64c-package.dtsi`, `rs780e-pch.dtsi`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.