arch/mips/boot/dts/mobileye/eyeq5.dtsi
Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/mobileye/eyeq5.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/boot/dts/mobileye/eyeq5.dtsi- Extension
.dtsi- Size
- 9354 bytes
- Lines
- 357
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/mips-gic.hdt-bindings/clock/mobileye,eyeq5-clk.heyeq5-pins.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
/*
* Copyright 2023 Mobileye Vision Technologies Ltd.
*/
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "img,i6500";
reg = <0>;
clocks = <&olb EQ5C_CPU_CORE0>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* These reserved memory regions are also defined in bootmanager
* for configuring inbound translation for BARS, don't change
* these without syncing with bootmanager
*/
shmem0_reserved: shmem@804000000 {
reg = <0x8 0x04000000 0x0 0x1000000>;
};
shmem1_reserved: shmem@805000000 {
reg = <0x8 0x05000000 0x0 0x1000000>;
};
pci0_msi_reserved: pci0-msi@806000000 {
reg = <0x8 0x06000000 0x0 0x100000>;
};
pci1_msi_reserved: pci1-msi@806100000 {
reg = <0x8 0x06100000 0x0 0x100000>;
};
mini_coredump0_reserved: mini-coredump0@806200000 {
reg = <0x8 0x06200000 0x0 0x100000>;
};
mhm_reserved_0: the-mhm-reserved-0@0 {
reg = <0x8 0x00000000 0x0 0x0000800>;
};
nvram@461fe00 {
compatible = "mobileye,eyeq5-bootloader-config", "nvmem-rmem";
reg = <0x0 0x0461fe00 0x0 0x200>;
#address-cells = <1>;
#size-cells = <1>;
no-map;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eth0_mac: mac@7c {
reg = <0x7c 0x6>;
};
eth1_mac: mac@82 {
reg = <0x82 0x6>;
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/mips-gic.h`, `dt-bindings/clock/mobileye,eyeq5-clk.h`, `eyeq5-pins.dtsi`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.