arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi
Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi- Extension
.dtsi- Size
- 2662 bytes
- Lines
- 126
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
* pin configuration node per function.
*/
&olb {
timer0_pins: timer0-pins {
function = "timer0";
pins = "PA0", "PA1";
};
timer1_pins: timer1-pins {
function = "timer1";
pins = "PA2", "PA3";
};
timer2_pins: timer2-pins {
function = "timer2";
pins = "PA4", "PA5";
};
pps0_pins: pps0-pin {
function = "timer2";
pins = "PA4";
};
pps1_pins: pps1-pin {
function = "timer2";
pins = "PA5";
};
timer5_ext_pins: timer5-ext-pins {
function = "timer5";
pins = "PA6", "PA7", "PA8", "PA9";
};
timer5_ext_input_pins: timer5-ext-input-pins {
function = "timer5";
pins = "PA6", "PA7";
};
timer5_ext_incap_a_pins: timer5-ext-incap-a-pin {
function = "timer5";
pins = "PA6";
};
timer5_ext_incap_b_pins: timer5-ext-incap-b-pin {
function = "timer5";
pins = "PA7";
};
can0_pins: can0-pins {
function = "can0";
pins = "PA14", "PA15";
};
can1_pins: can1-pins {
function = "can1";
pins = "PA16", "PA17";
};
uart0_pins: uart0-pins {
function = "uart0";
pins = "PA10", "PA11";
};
uart1_pins: uart1-pins {
function = "uart1";
pins = "PA12", "PA13";
};
spi0_pins: spi0-pins {
function = "spi0";
pins = "PA18", "PA19", "PA20", "PA21", "PA22";
};
spi1_pins: spi1-pins {
function = "spi1";
pins = "PA23", "PA24", "PA25", "PA26", "PA27";
};
spi1_slave_pins: spi1-slave-pins {
function = "spi1";
Annotation
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.