arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi- Extension
.dtsi- Size
- 4190 bytes
- Lines
- 171
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/mips-gic.hdt-bindings/clock/mobileye,eyeq6lplus-clk.heyeq6lplus-pins.dtsi
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/*
* Copyright 2025 Mobileye Vision Technologies Ltd.
*/
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "img,i6500";
reg = <0>;
clocks = <&olb EQ6LPC_CPU_OCC>;
};
};
cpu_intc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
coherency-manager {
compatible = "mobileye,eyeq6-cm";
};
xtal: clock-30000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <30000000>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
olb: system-controller@e8400000 {
compatible = "mobileye,eyeq6lplus-olb", "syscon";
reg = <0 0xe8400000 0x0 0x80000>;
#reset-cells = <2>;
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
};
ospi: spi@e8800000 {
compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0xe8800000 0x0 0x100000>,
<0 0xb0000000 0x0 0x30000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <128>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&olb EQ6LPC_PER_OSPI>;
status = "disabled";
};
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/mips-gic.h`, `dt-bindings/clock/mobileye,eyeq6lplus-clk.h`, `eyeq6lplus-pins.dtsi`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.