arch/mips/boot/dts/mti/sead3.dts
Source file repositories/reference/linux-study-clean/arch/mips/boot/dts/mti/sead3.dts
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/boot/dts/mti/sead3.dts- Extension
.dts- Size
- 4991 bytes
- Lines
- 260
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
dt-bindings/interrupt-controller/mips-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/memreserve/ 0x00000000 0x00001000; // reserved
/memreserve/ 0x00001000 0x000ef000; // ROM data
/memreserve/ 0x000f0000 0x004cc000; // reserved
#include <dt-bindings/interrupt-controller/mips-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,sead-3";
model = "MIPS SEAD-3";
chosen {
stdout-path = "serial1:115200";
};
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
cpu@0 {
compatible = "mti,mips14KEc", "mti,mips14Kc";
};
};
memory {
device_type = "memory";
reg = <0x0 0x08000000>;
};
cpu_intc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
gic: interrupt-controller@1b1c0000 {
compatible = "mti,gic";
reg = <0x1b1c0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
/*
* Declare the interrupt-parent even though the mti,gic
* binding doesn't require it, such that the kernel can
* figure out that cpu_intc is the root interrupt
* controller & should be probed first.
*/
interrupt-parent = <&cpu_intc>;
};
usb@1b200000 {
compatible = "generic-ehci";
reg = <0x1b200000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
has-transaction-translator;
};
flash@1c000000 {
compatible = "intel,28f128j3", "cfi-flash";
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/mips-gic.h`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.