arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

Source file repositories/reference/linux-study-clean/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c

File Facts

System
Linux kernel
Corpus path
arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
Extension
.c
Size
15844 bytes
Lines
516
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

if (pcsx_miscx_ctl_reg.s.mac_phy) {
			/* PHY Mode */
			union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg;
			pcsx_sgmx_an_adv_reg.u64 =
			    cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG
					  (index, interface));
			pcsx_sgmx_an_adv_reg.s.link = 1;
			pcsx_sgmx_an_adv_reg.s.dup = 1;
			pcsx_sgmx_an_adv_reg.s.speed = 2;
			cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG
				       (index, interface),
				       pcsx_sgmx_an_adv_reg.u64);
		} else {
			/* MAC Mode - Nothing to do */
		}
	}
	return 0;
}

/**
 * Initialize the SERTES link for the first time or after a loss
 * of link.
 *
 * @interface: Interface to init
 * @index:     Index of prot on the interface
 *
 * Returns Zero on success, negative on failure
 */
static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
{
	union cvmx_pcsx_mrx_control_reg control_reg;

	/*
	 * Take PCS through a reset sequence.
	 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero.
	 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the
	 * value of the other PCS*_MR*_CONTROL_REG bits).  Read
	 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to
	 * zero.
	 */
	control_reg.u64 =
	    cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
	if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
		control_reg.s.reset = 1;
		cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
			       control_reg.u64);
		if (CVMX_WAIT_FOR_FIELD64
		    (CVMX_PCSX_MRX_CONTROL_REG(index, interface),
		     union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) {
			cvmx_dprintf("SGMII%d: Timeout waiting for port %d "
				     "to finish reset\n",
			     interface, index);
			return -1;
		}
	}

	/*
	 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh
	 * sgmii negotiation starts.
	 */
	control_reg.s.rst_an = 1;
	control_reg.s.an_en = 1;
	control_reg.s.pwr_dn = 0;
	cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
		       control_reg.u64);

	/*
	 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
	 * that sgmii autonegotiation is complete. In MAC mode this
	 * isn't an ethernet link, but a link between Octeon and the
	 * PHY.
	 */
	if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
	    CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface),
				  union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1,
				  10000)) {
		/* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */
		return -1;
	}
	return 0;
}

/**
 * Configure an SGMII link to the specified speed after the SERTES
 * link is up.
 *
 * @interface: Interface to init
 * @index:     Index of prot on the interface
 * @link_info: Link state to configure
 *

Annotation

Implementation Notes