arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
Source file repositories/reference/linux-study-clean/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c- Extension
.c- Size
- 14295 bytes
- Lines
- 379
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/octeon/octeon.hasm/octeon/cvmx-gmxx-defs.hasm/octeon/cvmx-pcsx-defs.hasm/octeon/cvmx-pcsxx-defs.hasm/octeon/cvmx-spxx-defs.hasm/octeon/cvmx-stxx-defs.h
Detected Declarations
function __cvmx_interrupt_gmxx_rxx_int_en_enablefunction __cvmx_interrupt_pcsx_intx_en_reg_enablefunction __cvmx_interrupt_pcsxx_int_en_reg_enablefunction __cvmx_interrupt_spxx_int_msk_enablefunction __cvmx_interrupt_stxx_int_msk_enable
Annotated Snippet
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsx-defs.h>
#include <asm/octeon/cvmx-pcsxx-defs.h>
#include <asm/octeon/cvmx-spxx-defs.h>
#include <asm/octeon/cvmx-stxx-defs.h>
#ifndef PRINT_ERROR
#define PRINT_ERROR(format, ...)
#endif
/**
* __cvmx_interrupt_gmxx_rxx_int_en_enable - enable all interrupt bits in cvmx_gmxx_rxx_int_en_t
* @index: interrupt register offset
* @block: interrupt register block_id
*/
void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
{
union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),
cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
gmx_rx_int_en.u64 = 0;
if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
/* Skipping gmx_rx_int_en.s.reserved_29_63 */
gmx_rx_int_en.s.hg2cc = 1;
gmx_rx_int_en.s.hg2fld = 1;
gmx_rx_int_en.s.undat = 1;
gmx_rx_int_en.s.uneop = 1;
gmx_rx_int_en.s.unsop = 1;
gmx_rx_int_en.s.bad_term = 1;
gmx_rx_int_en.s.bad_seq = 1;
gmx_rx_int_en.s.rem_fault = 1;
gmx_rx_int_en.s.loc_fault = 1;
gmx_rx_int_en.s.pause_drp = 1;
/* Skipping gmx_rx_int_en.s.reserved_16_18 */
/*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
gmx_rx_int_en.s.ovrerr = 1;
/* Skipping gmx_rx_int_en.s.reserved_9_9 */
gmx_rx_int_en.s.skperr = 1;
gmx_rx_int_en.s.rcverr = 1;
/* Skipping gmx_rx_int_en.s.reserved_5_6 */
/*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
gmx_rx_int_en.s.jabber = 1;
/* Skipping gmx_rx_int_en.s.reserved_2_2 */
gmx_rx_int_en.s.carext = 1;
/* Skipping gmx_rx_int_en.s.reserved_0_0 */
}
if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
/* Skipping gmx_rx_int_en.s.reserved_19_63 */
/*gmx_rx_int_en.s.phy_dupx = 1; */
/*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
gmx_rx_int_en.s.ovrerr = 1;
gmx_rx_int_en.s.niberr = 1;
gmx_rx_int_en.s.skperr = 1;
gmx_rx_int_en.s.rcverr = 1;
/*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
gmx_rx_int_en.s.alnerr = 1;
/*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
gmx_rx_int_en.s.jabber = 1;
gmx_rx_int_en.s.maxerr = 1;
gmx_rx_int_en.s.carext = 1;
gmx_rx_int_en.s.minerr = 1;
}
if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
/* Skipping gmx_rx_int_en.s.reserved_20_63 */
gmx_rx_int_en.s.pause_drp = 1;
/*gmx_rx_int_en.s.phy_dupx = 1; */
/*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
gmx_rx_int_en.s.ovrerr = 1;
gmx_rx_int_en.s.niberr = 1;
gmx_rx_int_en.s.skperr = 1;
gmx_rx_int_en.s.rcverr = 1;
Annotation
- Immediate include surface: `asm/octeon/octeon.h`, `asm/octeon/cvmx-gmxx-defs.h`, `asm/octeon/cvmx-pcsx-defs.h`, `asm/octeon/cvmx-pcsxx-defs.h`, `asm/octeon/cvmx-spxx-defs.h`, `asm/octeon/cvmx-stxx-defs.h`.
- Detected declarations: `function __cvmx_interrupt_gmxx_rxx_int_en_enable`, `function __cvmx_interrupt_pcsx_intx_en_reg_enable`, `function __cvmx_interrupt_pcsxx_int_en_reg_enable`, `function __cvmx_interrupt_spxx_int_msk_enable`, `function __cvmx_interrupt_stxx_int_msk_enable`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.