arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
Source file repositories/reference/linux-study-clean/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c- Extension
.c- Size
- 3814 bytes
- Lines
- 141
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/octeon/octeon.hasm/octeon/cvmx-asxx-defs.hasm/octeon/cvmx-gmxx-defs.h
Detected Declarations
function __cvmx_interrupt_asxx_enablefunction __cvmx_interrupt_gmxx_enable
Annotated Snippet
if (mode.s.en) {
switch (mode.cn52xx.mode) {
case 1: /* XAUI */
num_ports = 1;
break;
case 2: /* SGMII */
case 3: /* PICMG */
num_ports = 4;
break;
default: /* Disabled */
num_ports = 0;
break;
}
} else
num_ports = 0;
} else {
if (mode.s.en) {
if (OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)) {
/*
* SPI on CN38XX and CN58XX report all
* errors through port 0. RGMII needs
* to check all 4 ports
*/
if (mode.s.type)
num_ports = 1;
else
num_ports = 4;
} else {
/*
* CN30XX, CN31XX, and CN50XX have two
* or three ports. GMII and MII has 2,
* RGMII has three
*/
if (mode.s.type)
num_ports = 2;
else
num_ports = 3;
}
} else
num_ports = 0;
}
gmx_tx_int_en.u64 = 0;
if (num_ports) {
if (OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX))
gmx_tx_int_en.cn38xx.ncb_nxa = 1;
gmx_tx_int_en.s.pko_nxa = 1;
}
gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
for (index = 0; index < num_ports; index++)
__cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
}
Annotation
- Immediate include surface: `asm/octeon/octeon.h`, `asm/octeon/cvmx-asxx-defs.h`, `asm/octeon/cvmx-gmxx-defs.h`.
- Detected declarations: `function __cvmx_interrupt_asxx_enable`, `function __cvmx_interrupt_gmxx_enable`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.