arch/mips/cavium-octeon/executive/octeon-model.c

File Facts

System

Linux kernel

Corpus path

arch/mips/cavium-octeon/executive/octeon-model.c

Extension

.c

Size

11865 bytes

Lines

513

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.

Dependency Surface

• linux/string.h
• asm/octeon/octeon.h

Detected Declarations

• function cvmx_fuse_read_byte
• function octeon_model_get_string
• function octeon_model_get_string
• export __octeon_feature_bits

Annotated Snippet

if (l2d_fus3) {
			/*
			 * For some unknown reason, the 16 core one is
			 * called 37 instead of 36.
			 */
			if (num_cores >= 16)
				family = "37";
			else
				family = "36";
		} else
			family = "38";
		/*
		 * This series of chips didn't follow the standard
		 * pass numbering.
		 */
		switch (chip_id & 0xf) {
		case 0:
			strscpy(pass, "1.X");
			break;
		case 1:
			strscpy(pass, "2.X");
			break;
		case 3:
			strscpy(pass, "3.X");
			break;
		default:
			strscpy(pass, "X.X");
			break;
		}
		break;
	case 1:		/* CN31XX or CN3020 */
		if ((chip_id & 0x10) || l2d_fus3)
			family = "30";
		else
			family = "31";
		/*
		 * This series of chips didn't follow the standard
		 * pass numbering.
		 */
		switch (chip_id & 0xf) {
		case 0:
			strscpy(pass, "1.0");
			break;
		case 2:
			strscpy(pass, "1.1");
			break;
		default:
			strscpy(pass, "X.X");
			break;
		}
		break;
	case 2:		/* CN3010 or CN3005 */
		family = "30";
		/* A chip with half cache is an 05 */
		if (l2d_fus3)
			core_model = "05";
		/*
		 * This series of chips didn't follow the standard
		 * pass numbering.
		 */
		switch (chip_id & 0xf) {
		case 0:
			strscpy(pass, "1.0");
			break;
		case 2:
			strscpy(pass, "1.1");
			break;
		default:
			strscpy(pass, "X.X");
			break;
		}
		break;
	case 3:		/* CN58XX */
		family = "58";
		/* Special case. 4 core, half cache (CP with half cache) */
		if ((num_cores == 4) && l2d_fus3 && !strncmp(suffix, "CP", 2))
			core_model = "29";

		/* Pass 1 uses different encodings for pass numbers */
		if ((chip_id & 0xFF) < 0x8) {
			switch (chip_id & 0x3) {
			case 0:
				strscpy(pass, "1.0");
				break;
			case 1:
				strscpy(pass, "1.1");
				break;
			case 3:
				strscpy(pass, "1.2");
				break;

Annotation

• Immediate include surface: `linux/string.h`, `asm/octeon/octeon.h`.
• Detected declarations: `function cvmx_fuse_read_byte`, `function octeon_model_get_string`, `function octeon_model_get_string`, `export __octeon_feature_bits`.
• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: integration implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.