arch/mips/cavium-octeon/octeon-irq.c
Source file repositories/reference/linux-study-clean/arch/mips/cavium-octeon/octeon-irq.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/cavium-octeon/octeon-irq.c- Extension
.c- Size
- 75384 bytes
- Lines
- 3004
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/of_address.hlinux/interrupt.hlinux/irqdomain.hlinux/bitops.hlinux/of_irq.hlinux/percpu.hlinux/slab.hlinux/irq.hlinux/smp.hlinux/of.hasm/octeon/octeon.hasm/octeon/cvmx-ciu2-defs.hasm/octeon/cvmx-ciu3-defs.h
Detected Declarations
struct octeon_ciu3_infostruct octeon_irq_ciu_domain_datastruct octeon_ciu_chip_datastruct octeon_core_chip_datastruct octeon_irq_gpio_domain_datastruct octeon_irq_cib_host_datastruct octeon_irq_cib_chip_datafunction octeon_irq_set_ciu_mappingfunction octeon_irq_free_cdfunction octeon_irq_force_ciu_mappingfunction octeon_coreid_for_cpufunction octeon_cpu_for_coreidfunction octeon_irq_core_ackfunction octeon_irq_core_eoifunction octeon_irq_core_set_enable_localfunction octeon_irq_core_disablefunction octeon_irq_core_enablefunction octeon_irq_core_bus_lockfunction octeon_irq_core_bus_sync_unlockfunction octeon_irq_init_corefunction next_cpu_for_irqfunction octeon_irq_ciu_enablefunction octeon_irq_ciu_enable_localfunction octeon_irq_ciu_disable_localfunction octeon_irq_ciu_disable_allfunction for_each_online_cpufunction octeon_irq_ciu_enable_allfunction for_each_online_cpufunction octeon_irq_ciu_enable_v2function octeon_irq_ciu_enable_sum2function octeon_irq_ciu_disable_local_sum2function octeon_irq_ciu_ack_sum2function octeon_irq_ciu_disable_all_sum2function for_each_online_cpufunction octeon_irq_ciu_enable_local_v2function octeon_irq_ciu_disable_local_v2function octeon_irq_ciu_ackfunction octeon_irq_ciu_disable_all_v2function for_each_online_cpufunction octeon_irq_ciu_enable_all_v2function for_each_online_cpufunction octeon_irq_ciu_set_typefunction octeon_irq_gpio_setupfunction octeon_irq_ciu_enable_gpio_v2function octeon_irq_ciu_enable_gpiofunction octeon_irq_ciu_gpio_set_typefunction octeon_irq_ciu_disable_gpio_v2function octeon_irq_ciu_disable_gpio
Annotated Snippet
struct octeon_ciu3_info {
u64 ciu3_addr;
int node;
struct irq_domain *domain[MAX_CIU3_DOMAINS];
octeon_ciu3_intsn2hw_t intsn2hw[MAX_CIU3_DOMAINS];
};
/* Each ciu3 in the system uses its own data (one ciu3 per node) */
static struct octeon_ciu3_info *octeon_ciu3_info_per_node[4];
struct octeon_irq_ciu_domain_data {
int num_sum; /* number of sum registers (2 or 3). */
};
/* Register offsets from ciu3_addr */
#define CIU3_CONST 0x220
#define CIU3_IDT_CTL(_idt) ((_idt) * 8 + 0x110000)
#define CIU3_IDT_PP(_idt, _idx) ((_idt) * 32 + (_idx) * 8 + 0x120000)
#define CIU3_IDT_IO(_idt) ((_idt) * 8 + 0x130000)
#define CIU3_DEST_PP_INT(_pp_ip) ((_pp_ip) * 8 + 0x200000)
#define CIU3_DEST_IO_INT(_io) ((_io) * 8 + 0x210000)
#define CIU3_ISC_CTL(_intsn) ((_intsn) * 8 + 0x80000000)
#define CIU3_ISC_W1C(_intsn) ((_intsn) * 8 + 0x90000000)
#define CIU3_ISC_W1S(_intsn) ((_intsn) * 8 + 0xa0000000)
static __read_mostly int octeon_irq_ciu_to_irq[8][64];
struct octeon_ciu_chip_data {
union {
struct { /* only used for ciu3 */
u64 ciu3_addr;
unsigned int intsn;
};
struct { /* only used for ciu/ciu2 */
u8 line;
u8 bit;
};
};
int gpio_line;
int current_cpu; /* Next CPU expected to take this irq */
int ciu_node; /* NUMA node number of the CIU */
};
struct octeon_core_chip_data {
struct mutex core_irq_mutex;
bool current_en;
bool desired_en;
u8 bit;
};
#define MIPS_CORE_IRQ_LINES 8
static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
static int octeon_irq_set_ciu_mapping(int irq, int line, int bit, int gpio_line,
struct irq_chip *chip,
irq_flow_handler_t handler)
{
struct octeon_ciu_chip_data *cd;
cd = kzalloc_obj(*cd);
if (!cd)
return -ENOMEM;
irq_set_chip_and_handler(irq, chip, handler);
cd->line = line;
cd->bit = bit;
cd->gpio_line = gpio_line;
irq_set_chip_data(irq, cd);
octeon_irq_ciu_to_irq[line][bit] = irq;
return 0;
}
static void octeon_irq_free_cd(struct irq_domain *d, unsigned int irq)
{
struct irq_data *data = irq_get_irq_data(irq);
struct octeon_ciu_chip_data *cd = irq_data_get_irq_chip_data(data);
irq_set_chip_data(irq, NULL);
kfree(cd);
}
static int octeon_irq_force_ciu_mapping(struct irq_domain *domain,
int irq, int line, int bit)
{
struct device_node *of_node;
int ret;
Annotation
- Immediate include surface: `linux/of_address.h`, `linux/interrupt.h`, `linux/irqdomain.h`, `linux/bitops.h`, `linux/of_irq.h`, `linux/percpu.h`, `linux/slab.h`, `linux/irq.h`.
- Detected declarations: `struct octeon_ciu3_info`, `struct octeon_irq_ciu_domain_data`, `struct octeon_ciu_chip_data`, `struct octeon_core_chip_data`, `struct octeon_irq_gpio_domain_data`, `struct octeon_irq_cib_host_data`, `struct octeon_irq_cib_chip_data`, `function octeon_irq_set_ciu_mapping`, `function octeon_irq_free_cd`, `function octeon_irq_force_ciu_mapping`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.