arch/mips/cavium-octeon/smp.c
Source file repositories/reference/linux-study-clean/arch/mips/cavium-octeon/smp.c
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/cavium-octeon/smp.c- Extension
.c- Size
- 12654 bytes
- Lines
- 521
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/cpu.hlinux/delay.hlinux/smp.hlinux/interrupt.hlinux/kernel_stat.hlinux/sched.hlinux/sched/hotplug.hlinux/sched/task_stack.hlinux/init.hlinux/export.hlinux/kexec.hasm/mmu_context.hasm/time.hasm/setup.hasm/smp.hasm/octeon/octeon.hocteon_boot.h
Detected Declarations
function octeon_icache_flushfunction mailbox_interruptfunction octeon_send_ipi_singlefunction octeon_send_ipi_maskfunction octeon_smp_hotplug_setupfunction octeon_smp_setupfunction plat_post_relocationfunction octeon_boot_secondaryfunction octeon_init_secondaryfunction octeon_prepare_cpusfunction octeon_smp_finishfunction octeon_cpu_disablefunction octeon_cpu_diefunction play_deadfunction start_after_resetfunction octeon_update_boot_vectorfunction register_cavium_notifierfunction octeon_78xx_reched_interruptfunction octeon_78xx_call_function_interruptfunction octeon_78xx_icache_flush_interruptfunction octeon_78xx_prepare_cpusfunction octeon_78xx_send_ipi_singlefunction octeon_78xx_send_ipi_maskfunction octeon_setup_smpexport octeon_bootloader_entry_addr
Annotated Snippet
if (action & 1) {
void (*fn)(void) = octeon_message_functions[i];
if (fn)
fn();
}
action >>= 1;
i++;
}
return IRQ_HANDLED;
}
/*
* Cause the function described by call_data to be executed on the passed
* cpu. When the function has finished, increment the finished field of
* call_data.
*/
void octeon_send_ipi_single(int cpu, unsigned int action)
{
int coreid = cpu_logical_map(cpu);
/*
pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
coreid, action);
*/
cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}
static inline void octeon_send_ipi_mask(const struct cpumask *mask,
unsigned int action)
{
unsigned int i;
for_each_cpu(i, mask)
octeon_send_ipi_single(i, action);
}
/*
* Detect available CPUs, populate cpu_possible_mask
*/
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
struct linux_app_boot_info *labi;
if (!setup_max_cpus)
return;
labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
if (labi->labi_signature != LABI_SIGNATURE) {
pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
return;
}
octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}
static void __init octeon_smp_setup(void)
{
const int coreid = cvmx_get_core_num();
int cpus;
int id;
struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
#ifdef CONFIG_HOTPLUG_CPU
int core_mask = octeon_get_boot_coremask();
unsigned int num_cores = cvmx_octeon_num_cores();
#endif
/* The present CPUs are initially just the boot cpu (CPU 0). */
for (id = 0; id < NR_CPUS; id++) {
set_cpu_possible(id, id == 0);
set_cpu_present(id, id == 0);
}
__cpu_number_map[coreid] = 0;
__cpu_logical_map[0] = coreid;
/* The present CPUs get the lowest CPU numbers. */
cpus = 1;
for (id = 0; id < NR_CPUS; id++) {
if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
set_cpu_possible(cpus, true);
set_cpu_present(cpus, true);
__cpu_number_map[id] = cpus;
__cpu_logical_map[cpus] = id;
cpus++;
}
}
Annotation
- Immediate include surface: `linux/cpu.h`, `linux/delay.h`, `linux/smp.h`, `linux/interrupt.h`, `linux/kernel_stat.h`, `linux/sched.h`, `linux/sched/hotplug.h`, `linux/sched/task_stack.h`.
- Detected declarations: `function octeon_icache_flush`, `function mailbox_interrupt`, `function octeon_send_ipi_single`, `function octeon_send_ipi_mask`, `function octeon_smp_hotplug_setup`, `function octeon_smp_setup`, `function plat_post_relocation`, `function octeon_boot_secondary`, `function octeon_init_secondary`, `function octeon_prepare_cpus`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: integration implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.