arch/mips/dec/int-handler.S
Source file repositories/reference/linux-study-clean/arch/mips/dec/int-handler.S
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/dec/int-handler.S- Extension
.S- Size
- 7770 bytes
- Lines
- 312
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: arch/mips
- Status
- atlas-only
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/addrspace.hasm/asm.hasm/mipsregs.hasm/regdef.hasm/stackframe.hasm/dec/interrupts.hasm/dec/ioasic_addrs.hasm/dec/ioasic_ints.hasm/dec/kn01.hasm/dec/kn02.hasm/dec/kn02xa.hasm/dec/kn03.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#include <asm/addrspace.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/dec/interrupts.h>
#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/ioasic_ints.h>
#include <asm/dec/kn01.h>
#include <asm/dec/kn02.h>
#include <asm/dec/kn02xa.h>
#include <asm/dec/kn03.h>
#define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
#define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
#define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
.text
.set noreorder
/*
* plat_irq_dispatch: Interrupt handler for DECstations
*
* We follow the model in the Indy interrupt code by David Miller, where he
* says: a lot of complication here is taken away because:
*
* 1) We handle one interrupt and return, sitting in a loop
* and moving across all the pending IRQ bits in the cause
* register is _NOT_ the answer, the common case is one
* pending IRQ so optimize in that direction.
*
* 2) We need not check against bits in the status register
* IRQ mask, that would make this routine slow as hell.
*
* 3) Linux only thinks in terms of all IRQs on or all IRQs
* off, nothing in between like BSD spl() brain-damage.
*
* Furthermore, the IRQs on the DECstations look basically (barring
* software IRQs which we don't use at all) like...
*
* DS2100/3100's, aka kn01, aka Pmax:
*
* MIPS IRQ Source
* -------- ------
* 0 Software (ignored)
* 1 Software (ignored)
* 2 SCSI
* 3 Lance Ethernet
* 4 DZ11 serial
* 5 RTC
* 6 Memory Controller & Video
* 7 FPU
*
* DS5000/200, aka kn02, aka 3max:
*
* MIPS IRQ Source
* -------- ------
* 0 Software (ignored)
* 1 Software (ignored)
* 2 TurboChannel
* 3 RTC
* 4 Reserved
* 5 Memory Controller
* 6 Reserved
* 7 FPU
*
* DS5000/1xx's, aka kn02ba, aka 3min:
*
* MIPS IRQ Source
* -------- ------
Annotation
- Immediate include surface: `asm/addrspace.h`, `asm/asm.h`, `asm/mipsregs.h`, `asm/regdef.h`, `asm/stackframe.h`, `asm/dec/interrupts.h`, `asm/dec/ioasic_addrs.h`, `asm/dec/ioasic_ints.h`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.