arch/mips/dec/time.c

Source file repositories/reference/linux-study-clean/arch/mips/dec/time.c

File Facts

System
Linux kernel
Corpus path
arch/mips/dec/time.c
Extension
.c
Size
4945 bytes
Lines
173
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
			real_seconds = bin2bcd(real_seconds);
			real_minutes = bin2bcd(real_minutes);
		}
		CMOS_WRITE(real_seconds, RTC_SECONDS);
		CMOS_WRITE(real_minutes, RTC_MINUTES);
	} else {
		printk_once(KERN_NOTICE
		       "set_rtc_mmss: can't update from %d to %d\n",
		       cmos_minutes, real_minutes);
		retval = -1;
	}

	/* The following flags have to be released exactly in this order,
	 * otherwise the DS1287 will not reset the oscillator and will not
	 * update precisely 500 ms later.  You won't find this mentioned
	 * in the Dallas Semiconductor data sheets, but who believes data
	 * sheets anyway ...                           -- Markus Kuhn
	 */
	CMOS_WRITE(save_control, RTC_CONTROL);
	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
	spin_unlock(&rtc_lock);

	return retval;
}

void __init plat_time_init(void)
{
	int ioasic_clock = 0;
	u32 start, end;
	int i = HZ / 8;

	/* Set up the rate of periodic DS1287 interrupts. */
	ds1287_set_base_clock(HZ);

	/* On some I/O ASIC systems we have the I/O ASIC's counter.  */
	if (IOASIC)
		ioasic_clock = dec_ioasic_clocksource_init() == 0;
	if (cpu_has_counter) {
		ds1287_timer_state();
		while (!ds1287_timer_state())
			;

		start = read_c0_count();

		while (i--)
			while (!ds1287_timer_state())
				;

		end = read_c0_count();

		mips_hpt_frequency = (end - start) * 8;
		printk(KERN_INFO "MIPS counter frequency %dHz\n",
			mips_hpt_frequency);

		/*
		 * All R4k DECstations suffer from the CP0 Count erratum,
		 * so we can't use the timer as a clock source, and a clock
		 * event both at a time.  An accurate wall clock is more
		 * important than a high-precision interval timer so only
		 * use the timer as a clock source, and not a clock event
		 * if there's no I/O ASIC counter available to serve as a
		 * clock source.
		 */
		if (!ioasic_clock) {
			init_r4k_clocksource();
			mips_hpt_frequency = 0;
		}
	}

	ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
}

Annotation

Implementation Notes