arch/mips/include/asm/dec/ioasic_addrs.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/dec/ioasic_addrs.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/dec/ioasic_addrs.h
Extension
.h
Size
6475 bytes
Lines
153
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define __ASM_MIPS_DEC_IOASIC_ADDRS_H

#define IOASIC_SLOT_SIZE 0x00040000

/*
 * Address ranges decoded by the I/O ASIC for onboard devices.
 */
#define IOASIC_SYS_ROM	(0*IOASIC_SLOT_SIZE)	/* system board ROM */
#define IOASIC_IOCTL	(1*IOASIC_SLOT_SIZE)	/* I/O ASIC */
#define IOASIC_ESAR	(2*IOASIC_SLOT_SIZE)	/* LANCE MAC address chip */
#define IOASIC_LANCE	(3*IOASIC_SLOT_SIZE)	/* LANCE Ethernet */
#define IOASIC_SCC0	(4*IOASIC_SLOT_SIZE)	/* SCC #0 */
#define IOASIC_VDAC_HI	(5*IOASIC_SLOT_SIZE)	/* VDAC (maxine) */
#define IOASIC_SCC1	(6*IOASIC_SLOT_SIZE)	/* SCC #1 (3min, 3max+) */
#define IOASIC_VDAC_LO	(7*IOASIC_SLOT_SIZE)	/* VDAC (maxine) */
#define IOASIC_TOY	(8*IOASIC_SLOT_SIZE)	/* RTC */
#define IOASIC_ISDN	(9*IOASIC_SLOT_SIZE)	/* ISDN (maxine) */
#define IOASIC_ERRADDR	(9*IOASIC_SLOT_SIZE)	/* bus error address (3max+) */
#define IOASIC_CHKSYN	(10*IOASIC_SLOT_SIZE)	/* ECC syndrome (3max+) */
#define IOASIC_ACC_BUS	(10*IOASIC_SLOT_SIZE)	/* ACCESS.bus (maxine) */
#define IOASIC_MCR	(11*IOASIC_SLOT_SIZE)	/* memory control (3max+) */
#define IOASIC_FLOPPY	(11*IOASIC_SLOT_SIZE)	/* FDC (maxine) */
#define IOASIC_SCSI	(12*IOASIC_SLOT_SIZE)	/* ASC SCSI */
#define IOASIC_FDC_DMA	(13*IOASIC_SLOT_SIZE)	/* FDC DMA (maxine) */
#define IOASIC_SCSI_DMA	(14*IOASIC_SLOT_SIZE)	/* ??? */
#define IOASIC_RES_15	(15*IOASIC_SLOT_SIZE)	/* unused? */


/*
 * Offsets for I/O ASIC registers
 * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
 */
					/* all systems */
#define IO_REG_SCSI_DMA_P	0x00	/* SCSI DMA Pointer */
#define IO_REG_SCSI_DMA_BP	0x10	/* SCSI DMA Buffer Pointer */
#define IO_REG_LANCE_DMA_P	0x20	/* LANCE DMA Pointer */
#define IO_REG_SCC0A_T_DMA_P	0x30	/* SCC0A Transmit DMA Pointer */
#define IO_REG_SCC0A_R_DMA_P	0x40	/* SCC0A Receive DMA Pointer */

					/* except Maxine */
#define IO_REG_SCC1A_T_DMA_P	0x50	/* SCC1A Transmit DMA Pointer */
#define IO_REG_SCC1A_R_DMA_P	0x60	/* SCC1A Receive DMA Pointer */

					/* Maxine */
#define IO_REG_AB_T_DMA_P	0x50	/* ACCESS.bus Transmit DMA Pointer */
#define IO_REG_AB_R_DMA_P	0x60	/* ACCESS.bus Receive DMA Pointer */
#define IO_REG_FLOPPY_DMA_P	0x70	/* Floppy DMA Pointer */
#define IO_REG_ISDN_T_DMA_P	0x80	/* ISDN Transmit DMA Pointer */
#define IO_REG_ISDN_T_DMA_BP	0x90	/* ISDN Transmit DMA Buffer Pointer */
#define IO_REG_ISDN_R_DMA_P	0xa0	/* ISDN Receive DMA Pointer */
#define IO_REG_ISDN_R_DMA_BP	0xb0	/* ISDN Receive DMA Buffer Pointer */

					/* all systems */
#define IO_REG_DATA_0		0xc0	/* System Data Buffer 0 */
#define IO_REG_DATA_1		0xd0	/* System Data Buffer 1 */
#define IO_REG_DATA_2		0xe0	/* System Data Buffer 2 */
#define IO_REG_DATA_3		0xf0	/* System Data Buffer 3 */

					/* all systems */
#define IO_REG_SSR		0x100	/* System Support Register */
#define IO_REG_SIR		0x110	/* System Interrupt Register */
#define IO_REG_SIMR		0x120	/* System Interrupt Mask Reg. */
#define IO_REG_SAR		0x130	/* System Address Register */

					/* Maxine */
#define IO_REG_ISDN_T_DATA	0x140	/* ISDN Xmit Data Register */
#define IO_REG_ISDN_R_DATA	0x150	/* ISDN Receive Data Register */

					/* all systems */
#define IO_REG_LANCE_SLOT	0x160	/* LANCE I/O Slot Register */
#define IO_REG_SCSI_SLOT	0x170	/* SCSI Slot Register */
#define IO_REG_SCC0A_SLOT	0x180	/* SCC0A DMA Slot Register */

					/* except Maxine */
#define IO_REG_SCC1A_SLOT	0x190	/* SCC1A DMA Slot Register */

					/* Maxine */
#define IO_REG_AB_SLOT		0x190	/* ACCESS.bus DMA Slot Register */
#define IO_REG_FLOPPY_SLOT	0x1a0	/* Floppy Slot Register */

					/* all systems */
#define IO_REG_SCSI_SCR		0x1b0	/* SCSI Partial-Word DMA Control */
#define IO_REG_SCSI_SDR0	0x1c0	/* SCSI DMA Partial Word 0 */
#define IO_REG_SCSI_SDR1	0x1d0	/* SCSI DMA Partial Word 1 */
#define IO_REG_FCTR		0x1e0	/* Free-Running Counter */
#define IO_REG_RES_31		0x1f0	/* unused */


/*

Annotation

Implementation Notes