arch/mips/include/asm/ip32/mace.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/ip32/mace.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/ip32/mace.h
Extension
.h
Size
10742 bytes
Lines
366
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mace_pci {
	volatile unsigned int error_addr;
	volatile unsigned int error;
#define MACEPCI_ERROR_MASTER_ABORT		BIT(31)
#define MACEPCI_ERROR_TARGET_ABORT		BIT(30)
#define MACEPCI_ERROR_DATA_PARITY_ERR		BIT(29)
#define MACEPCI_ERROR_RETRY_ERR			BIT(28)
#define MACEPCI_ERROR_ILLEGAL_CMD		BIT(27)
#define MACEPCI_ERROR_SYSTEM_ERR		BIT(26)
#define MACEPCI_ERROR_INTERRUPT_TEST		BIT(25)
#define MACEPCI_ERROR_PARITY_ERR		BIT(24)
#define MACEPCI_ERROR_OVERRUN			BIT(23)
#define MACEPCI_ERROR_RSVD			BIT(22)
#define MACEPCI_ERROR_MEMORY_ADDR		BIT(21)
#define MACEPCI_ERROR_CONFIG_ADDR		BIT(20)
#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID	BIT(19)
#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID	BIT(18)
#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID	BIT(17)
#define MACEPCI_ERROR_RETRY_ADDR_VALID		BIT(16)
#define MACEPCI_ERROR_SIG_TABORT		BIT(4)
#define MACEPCI_ERROR_DEVSEL_MASK		0xc0
#define MACEPCI_ERROR_DEVSEL_FAST		0
#define MACEPCI_ERROR_DEVSEL_MED		0x40
#define MACEPCI_ERROR_DEVSEL_SLOW		0x80
#define MACEPCI_ERROR_FBB			BIT(1)
#define MACEPCI_ERROR_66MHZ			BIT(0)
	volatile unsigned int control;
#define MACEPCI_CONTROL_INT(x)			BIT(x)
#define MACEPCI_CONTROL_INT_MASK		0xff
#define MACEPCI_CONTROL_SERR_ENA		BIT(8)
#define MACEPCI_CONTROL_ARB_N6			BIT(9)
#define MACEPCI_CONTROL_PARITY_ERR		BIT(10)
#define MACEPCI_CONTROL_MRMRA_ENA		BIT(11)
#define MACEPCI_CONTROL_ARB_N3			BIT(12)
#define MACEPCI_CONTROL_ARB_N4			BIT(13)
#define MACEPCI_CONTROL_ARB_N5			BIT(14)
#define MACEPCI_CONTROL_PARK_LIU		BIT(15)
#define MACEPCI_CONTROL_INV_INT(x)		BIT(16+x)
#define MACEPCI_CONTROL_INV_INT_MASK		0x00ff0000
#define MACEPCI_CONTROL_OVERRUN_INT		BIT(24)
#define MACEPCI_CONTROL_PARITY_INT		BIT(25)
#define MACEPCI_CONTROL_SERR_INT		BIT(26)
#define MACEPCI_CONTROL_IT_INT			BIT(27)
#define MACEPCI_CONTROL_RE_INT			BIT(28)
#define MACEPCI_CONTROL_DPED_INT		BIT(29)
#define MACEPCI_CONTROL_TAR_INT			BIT(30)
#define MACEPCI_CONTROL_MAR_INT			BIT(31)
	volatile unsigned int rev;
	unsigned int _pad[0xcf8/4 - 4];
	volatile unsigned int config_addr;
	union {
		volatile unsigned char b[4];
		volatile unsigned short w[2];
		volatile unsigned int l;
	} config_data;
};
#define MACEPCI_LOW_MEMORY		0x1a000000
#define MACEPCI_LOW_IO			0x18000000
#define MACEPCI_SWAPPED_VIEW		0
#define MACEPCI_NATIVE_VIEW		0x40000000
#define MACEPCI_IO			0x80000000
#define MACEPCI_HI_MEMORY		0x280000000
#define MACEPCI_HI_IO			0x100000000

/*
 * Video interface
 */
struct mace_video {
	unsigned long xxx;	/* later... */
};

/*
 * Ethernet interface
 */
struct mace_ethernet {
	volatile u64 mac_ctrl;
	volatile unsigned long int_stat;
	volatile unsigned long dma_ctrl;
	volatile unsigned long timer;
	volatile unsigned long tx_int_al;
	volatile unsigned long rx_int_al;
	volatile unsigned long tx_info;
	volatile unsigned long tx_info_al;
	volatile unsigned long rx_buff;
	volatile unsigned long rx_buff_al1;
	volatile unsigned long rx_buff_al2;
	volatile unsigned long diag;
	volatile unsigned long phy_data;
	volatile unsigned long phy_regs;
	volatile unsigned long phy_trans_go;

Annotation

Implementation Notes