arch/mips/include/asm/mach-au1x00/au1000.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-au1x00/au1000.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-au1x00/au1000.h
Extension
.h
Size
38506 bytes
Lines
1215
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct alchemy_pci_platdata {
	int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
	int (*board_pci_idsel)(unsigned int devsel, int assert);
	/* bits to set/clear in PCI_CONFIG register */
	unsigned long pci_cfg_set;
	unsigned long pci_cfg_clr;
};

/* The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's
 * not used to select FIR/SIR mode on the transceiver but as a GPIO.
 * Instead a CPLD has to be told about the mode.  The driver calls the
 * set_phy_mode() function in addition to driving the IRFIRSEL pin.
 */
#define AU1000_IRDA_PHY_MODE_OFF	0
#define AU1000_IRDA_PHY_MODE_SIR	1
#define AU1000_IRDA_PHY_MODE_FIR	2

struct au1k_irda_platform_data {
	void (*set_phy_mode)(int mode);
};


/* Multifunction pins: Each of these pins can either be assigned to the
 * GPIO controller or a on-chip peripheral.
 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
 * assign one of these to either the GPIO controller or the device.
 */
enum au1300_multifunc_pins {
	/* wake-from-str pins 0-3 */
	AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
	AU1300_PIN_WAKE3,
	/* external clock sources for PSCs: 4-5 */
	AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
	/* 8bit MMC interface on SD0: 6-9 */
	AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
	AU1300_PIN_SD0DAT7,
	/* aux clk input for freqgen 3: 10 */
	AU1300_PIN_FG3AUX,
	/* UART1 pins: 11-18 */
	AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
	AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
	AU1300_PIN_U1RX, AU1300_PIN_U1TX,
	/* UART0 pins: 19-24 */
	AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
	AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
	/* UART2: 25-26 */
	AU1300_PIN_U2RX, AU1300_PIN_U2TX,
	/* UART3: 27-28 */
	AU1300_PIN_U3RX, AU1300_PIN_U3TX,
	/* LCD controller PWMs, ext pixclock: 29-31 */
	AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
	/* SD1 interface: 32-37 */
	AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
	AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
	/* SD2 interface: 38-43 */
	AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
	AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
	/* PSC0/1 clocks: 44-45 */
	AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
	/* PSCs: 46-49/50-53/54-57/58-61 */
	AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
	AU1300_PIN_PSC0D1,
	AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
	AU1300_PIN_PSC1D1,
	AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
	AU1300_PIN_PSC2D1,
	AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
	AU1300_PIN_PSC3D1,
	/* PCMCIA interface: 62-70 */
	AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
	AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
	AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
	/* camera interface H/V sync inputs: 71-72 */
	AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
	/* PSC2/3 clocks: 73-74 */
	AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
};

/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
extern void au1300_set_irq_priority(unsigned int irq, int p);
extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);

/* Au1300 allows to disconnect certain blocks from internal power supply */
enum au1300_vss_block {
	AU1300_VSS_MPE = 0,
	AU1300_VSS_BSA,
	AU1300_VSS_GPE,
	AU1300_VSS_MGP,

Annotation

Implementation Notes