arch/mips/include/asm/mach-au1x00/gpio-au1000.h
Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/include/asm/mach-au1x00/gpio-au1000.h- Extension
.h- Size
- 13943 bytes
- Lines
- 531
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/mach-au1x00/au1000.h
Detected Declarations
struct software_nodefunction au1000_gpio1_to_irqfunction au1000_gpio2_to_irqfunction au1000_irq_to_gpiofunction au1500_gpio1_to_irqfunction au1500_gpio2_to_irqfunction au1500_irq_to_gpiofunction au1100_gpio1_to_irqfunction au1100_gpio2_to_irqfunction au1100_irq_to_gpiofunction au1550_gpio1_to_irqfunction au1550_gpio2_to_irqfunction au1550_irq_to_gpiofunction au1200_gpio1_to_irqfunction au1200_gpio2_to_irqfunction au1200_irq_to_gpiofunction alchemy_gpio1_set_valuefunction alchemy_gpio1_get_valuefunction alchemy_gpio1_direction_inputfunction alchemy_gpio1_direction_outputfunction alchemy_gpio1_is_validfunction alchemy_gpio1_to_irqfunction alchemy_gpio1_input_enablefunction __alchemy_gpio2_mod_dirfunction alchemy_gpio2_set_valuefunction alchemy_gpio2_get_valuefunction alchemy_gpio2_direction_inputfunction alchemy_gpio2_direction_outputfunction alchemy_gpio2_is_validfunction alchemy_gpio2_to_irqfunction __alchemy_gpio2_mod_intfunction alchemy_gpio2_enable_intfunction alchemy_gpio2_enable_intfunction alchemy_gpio2_enablefunction alchemy_gpio2_disablefunction alchemy_gpio_direction_inputfunction alchemy_gpio_direction_outputfunction alchemy_gpio_get_valuefunction alchemy_gpio_set_valuefunction alchemy_gpio_is_validfunction alchemy_gpio_to_irqfunction alchemy_irq_to_gpio
Annotated Snippet
#ifndef _ALCHEMY_GPIO_AU1000_H_
#define _ALCHEMY_GPIO_AU1000_H_
#include <asm/mach-au1x00/au1000.h>
/* The default GPIO numberspace as documented in the Alchemy manuals.
* GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
*/
#define ALCHEMY_GPIO1_BASE 0
#define ALCHEMY_GPIO2_BASE 200
#define ALCHEMY_GPIO1_NUM 32
#define ALCHEMY_GPIO2_NUM 16
#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
/* GPIO1 registers within SYS_ area */
#define AU1000_SYS_TRIOUTRD 0x100
#define AU1000_SYS_TRIOUTCLR 0x100
#define AU1000_SYS_OUTPUTRD 0x108
#define AU1000_SYS_OUTPUTSET 0x108
#define AU1000_SYS_OUTPUTCLR 0x10C
#define AU1000_SYS_PINSTATERD 0x110
#define AU1000_SYS_PININPUTEN 0x110
/* register offsets within GPIO2 block */
#define AU1000_GPIO2_DIR 0x00
#define AU1000_GPIO2_OUTPUT 0x08
#define AU1000_GPIO2_PINSTATE 0x0C
#define AU1000_GPIO2_INTENABLE 0x10
#define AU1000_GPIO2_ENABLE 0x14
struct software_node;
extern const struct software_node alchemy_gpio1_node;
extern const struct software_node alchemy_gpio2_node;
static inline int au1000_gpio1_to_irq(int gpio)
{
return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
}
static inline int au1000_gpio2_to_irq(int gpio)
{
return -ENXIO;
}
static inline int au1000_irq_to_gpio(int irq)
{
if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
return -ENXIO;
}
static inline int au1500_gpio1_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO1_BASE;
switch (gpio) {
case 0 ... 15:
case 20:
case 23 ... 28: return MAKE_IRQ(1, gpio);
}
return -ENXIO;
}
static inline int au1500_gpio2_to_irq(int gpio)
{
gpio -= ALCHEMY_GPIO2_BASE;
switch (gpio) {
case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
}
return -ENXIO;
}
static inline int au1500_irq_to_gpio(int irq)
{
switch (irq) {
case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
case AU1500_GPIO20_INT:
case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
Annotation
- Immediate include surface: `asm/mach-au1x00/au1000.h`.
- Detected declarations: `struct software_node`, `function au1000_gpio1_to_irq`, `function au1000_gpio2_to_irq`, `function au1000_irq_to_gpio`, `function au1500_gpio1_to_irq`, `function au1500_gpio2_to_irq`, `function au1500_irq_to_gpio`, `function au1100_gpio1_to_irq`, `function au1100_gpio2_to_irq`, `function au1100_irq_to_gpio`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.