arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
Extension
.h
Size
38985 bytes
Lines
1069
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef BCM63XX_CPU_H_
#define BCM63XX_CPU_H_

#include <linux/types.h>
#include <linux/init.h>

/*
 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
 * compile time if only one CPU support is enabled (idea stolen from
 * arm mach-types)
 */
#define BCM3368_CPU_ID		0x3368
#define BCM6328_CPU_ID		0x6328
#define BCM6338_CPU_ID		0x6338
#define BCM6345_CPU_ID		0x6345
#define BCM6348_CPU_ID		0x6348
#define BCM6358_CPU_ID		0x6358
#define BCM6362_CPU_ID		0x6362
#define BCM6368_CPU_ID		0x6368

void __init bcm63xx_cpu_init(void);
u8 bcm63xx_get_cpu_rev(void);
unsigned int bcm63xx_get_cpu_freq(void);

static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)
{
	switch (cpu_id) {
#ifdef CONFIG_BCM63XX_CPU_3368
		case BCM3368_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6328
		case BCM6328_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6338
		case BCM6338_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6345
		case BCM6345_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6348
		case BCM6348_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6358
		case BCM6358_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6362
		case BCM6362_CPU_ID:
#endif

#ifdef CONFIG_BCM63XX_CPU_6368
		case BCM6368_CPU_ID:
#endif
		break;
	default:
		unreachable();
	}

	return cpu_id;
}

extern u16 bcm63xx_cpu_id;

static inline u16 __pure bcm63xx_get_cpu_id(void)
{
	const u16 cpu_id = bcm63xx_cpu_id;

	return __bcm63xx_get_cpu_id(cpu_id);
}

#define BCMCPU_IS_3368()	(bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
#define BCMCPU_IS_6328()	(bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
#define BCMCPU_IS_6338()	(bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
#define BCMCPU_IS_6345()	(bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
#define BCMCPU_IS_6348()	(bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
#define BCMCPU_IS_6358()	(bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
#define BCMCPU_IS_6362()	(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
#define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)

/*
 * While registers sets are (mostly) the same across 63xx CPU, base
 * address of these sets do change.
 */
enum bcm63xx_regs_set {
	RSET_DSL_LMEM = 0,

Annotation

Implementation Notes