arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
Extension
.h
Size
50869 bytes
Lines
1430
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef BCM63XX_REGS_H_
#define BCM63XX_REGS_H_

/*************************************************************************
 * _REG relative to RSET_PERF
 *************************************************************************/

/* Chip Identifier / Revision register */
#define PERF_REV_REG			0x0
#define REV_CHIPID_SHIFT		16
#define REV_CHIPID_MASK			(0xffff << REV_CHIPID_SHIFT)
#define REV_REVID_SHIFT			0
#define REV_REVID_MASK			(0xff << REV_REVID_SHIFT)

/* Clock Control register */
#define PERF_CKCTL_REG			0x4

#define CKCTL_3368_MAC_EN		(1 << 3)
#define CKCTL_3368_TC_EN		(1 << 5)
#define CKCTL_3368_US_TOP_EN		(1 << 6)
#define CKCTL_3368_DS_TOP_EN		(1 << 7)
#define CKCTL_3368_APM_EN		(1 << 8)
#define CKCTL_3368_SPI_EN		(1 << 9)
#define CKCTL_3368_USBS_EN		(1 << 10)
#define CKCTL_3368_BMU_EN		(1 << 11)
#define CKCTL_3368_PCM_EN		(1 << 12)
#define CKCTL_3368_NTP_EN		(1 << 13)
#define CKCTL_3368_ACP_B_EN		(1 << 14)
#define CKCTL_3368_ACP_A_EN		(1 << 15)
#define CKCTL_3368_EMUSB_EN		(1 << 17)
#define CKCTL_3368_ENET0_EN		(1 << 18)
#define CKCTL_3368_ENET1_EN		(1 << 19)
#define CKCTL_3368_USBU_EN		(1 << 20)
#define CKCTL_3368_EPHY_EN		(1 << 21)

#define CKCTL_3368_ALL_SAFE_EN		(CKCTL_3368_MAC_EN | \
					 CKCTL_3368_TC_EN | \
					 CKCTL_3368_US_TOP_EN | \
					 CKCTL_3368_DS_TOP_EN | \
					 CKCTL_3368_APM_EN | \
					 CKCTL_3368_SPI_EN | \
					 CKCTL_3368_USBS_EN | \
					 CKCTL_3368_BMU_EN | \
					 CKCTL_3368_PCM_EN | \
					 CKCTL_3368_NTP_EN | \
					 CKCTL_3368_ACP_B_EN | \
					 CKCTL_3368_ACP_A_EN | \
					 CKCTL_3368_EMUSB_EN | \
					 CKCTL_3368_USBU_EN)

#define CKCTL_6328_PHYMIPS_EN		(1 << 0)
#define CKCTL_6328_ADSL_QPROC_EN	(1 << 1)
#define CKCTL_6328_ADSL_AFE_EN		(1 << 2)
#define CKCTL_6328_ADSL_EN		(1 << 3)
#define CKCTL_6328_MIPS_EN		(1 << 4)
#define CKCTL_6328_SAR_EN		(1 << 5)
#define CKCTL_6328_PCM_EN		(1 << 6)
#define CKCTL_6328_USBD_EN		(1 << 7)
#define CKCTL_6328_USBH_EN		(1 << 8)
#define CKCTL_6328_HSSPI_EN		(1 << 9)
#define CKCTL_6328_PCIE_EN		(1 << 10)
#define CKCTL_6328_ROBOSW_EN		(1 << 11)

#define CKCTL_6328_ALL_SAFE_EN		(CKCTL_6328_PHYMIPS_EN |	\
					CKCTL_6328_ADSL_QPROC_EN |	\
					CKCTL_6328_ADSL_AFE_EN |	\
					CKCTL_6328_ADSL_EN |		\
					CKCTL_6328_SAR_EN  |		\
					CKCTL_6328_PCM_EN  |		\
					CKCTL_6328_USBD_EN |		\
					CKCTL_6328_USBH_EN |		\
					CKCTL_6328_ROBOSW_EN |		\
					CKCTL_6328_PCIE_EN)

#define CKCTL_6338_ADSLPHY_EN		(1 << 0)
#define CKCTL_6338_MPI_EN		(1 << 1)
#define CKCTL_6338_DRAM_EN		(1 << 2)
#define CKCTL_6338_ENET_EN		(1 << 4)
#define CKCTL_6338_USBS_EN		(1 << 4)
#define CKCTL_6338_SAR_EN		(1 << 5)
#define CKCTL_6338_SPI_EN		(1 << 9)

#define CKCTL_6338_ALL_SAFE_EN		(CKCTL_6338_ADSLPHY_EN |	\
					CKCTL_6338_MPI_EN |		\
					CKCTL_6338_ENET_EN |		\
					CKCTL_6338_SAR_EN |		\
					CKCTL_6338_SPI_EN)

/* BCM6345 clock bits are shifted by 16 on the left, because of the test
 * control register which is 16-bits wide. That way we do not have any

Annotation

Implementation Notes