arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536.h
Extension
.h
Size
7400 bytes
Lines
307
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _CS5536_H
#define _CS5536_H

#include <linux/types.h>

extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
extern void _wrmsr(u32 msr, u32 hi, u32 lo);

/*
 * MSR module base
 */
#define CS5536_SB_MSR_BASE	(0x00000000)
#define CS5536_GLIU_MSR_BASE	(0x10000000)
#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
#define CS5536_USB_MSR_BASE	(0x40000000)
#define CS5536_IDE_MSR_BASE	(0x60000000)
#define CS5536_DIVIL_MSR_BASE	(0x80000000)
#define CS5536_ACC_MSR_BASE	(0xa0000000)
#define CS5536_UNUSED_MSR_BASE	(0xc0000000)
#define CS5536_GLCP_MSR_BASE	(0xe0000000)

#define SB_MSR_REG(offset)	(CS5536_SB_MSR_BASE	| (offset))
#define GLIU_MSR_REG(offset)	(CS5536_GLIU_MSR_BASE	| (offset))
#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
#define USB_MSR_REG(offset)	(CS5536_USB_MSR_BASE	| (offset))
#define IDE_MSR_REG(offset)	(CS5536_IDE_MSR_BASE	| (offset))
#define DIVIL_MSR_REG(offset)	(CS5536_DIVIL_MSR_BASE	| (offset))
#define ACC_MSR_REG(offset)	(CS5536_ACC_MSR_BASE	| (offset))
#define UNUSED_MSR_REG(offset)	(CS5536_UNUSED_MSR_BASE | (offset))
#define GLCP_MSR_REG(offset)	(CS5536_GLCP_MSR_BASE	| (offset))

/*
 * BAR SPACE OF VIRTUAL PCI :
 * range for pci probe use, length is the actual size.
 */
/* IO space for all DIVIL modules */
#define CS5536_IRQ_RANGE	0xffffffe0 /* USERD FOR PCI PROBE */
#define CS5536_IRQ_LENGTH	0x20	/* THE REGS ACTUAL LENGTH */
#define CS5536_SMB_RANGE	0xfffffff8
#define CS5536_SMB_LENGTH	0x08
#define CS5536_GPIO_RANGE	0xffffff00
#define CS5536_GPIO_LENGTH	0x100
#define CS5536_MFGPT_RANGE	0xffffffc0
#define CS5536_MFGPT_LENGTH	0x40
#define CS5536_ACPI_RANGE	0xffffffe0
#define CS5536_ACPI_LENGTH	0x20
#define CS5536_PMS_RANGE	0xffffff80
#define CS5536_PMS_LENGTH	0x80
/* IO space for IDE */
#define CS5536_IDE_RANGE	0xfffffff0
#define CS5536_IDE_LENGTH	0x10
/* IO space for ACC */
#define CS5536_ACC_RANGE	0xffffff80
#define CS5536_ACC_LENGTH	0x80
/* MEM space for ALL USB modules */
#define CS5536_OHCI_RANGE	0xfffff000
#define CS5536_OHCI_LENGTH	0x1000
#define CS5536_EHCI_RANGE	0xfffff000
#define CS5536_EHCI_LENGTH	0x1000

/*
 * PCI MSR ACCESS
 */
#define PCI_MSR_CTRL		0xF0
#define PCI_MSR_ADDR		0xF4
#define PCI_MSR_DATA_LO		0xF8
#define PCI_MSR_DATA_HI		0xFC

/**************** MSR *****************************/

/*
 * GLIU STANDARD MSR
 */
#define GLIU_CAP		0x00
#define GLIU_CONFIG		0x01
#define GLIU_SMI		0x02
#define GLIU_ERROR		0x03
#define GLIU_PM			0x04
#define GLIU_DIAG		0x05

/*
 * GLIU SPEC. MSR
 */
#define GLIU_P2D_BM0		0x20
#define GLIU_P2D_BM1		0x21
#define GLIU_P2D_BM2		0x22
#define GLIU_P2D_BMK0		0x23
#define GLIU_P2D_BMK1		0x24
#define GLIU_P2D_BM3		0x25
#define GLIU_P2D_BM4		0x26

Annotation

Implementation Notes