arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-loongson2ef/cs5536/cs5536_pci.h
Extension
.h
Size
4613 bytes
Lines
174
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _CS5536_PCI_H
#define _CS5536_PCI_H

#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci_regs.h>

extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
extern u32 cs5536_pci_conf_read4(int function, int reg);

extern void pci_ehci_write_reg(int reg, u32 value);
extern u32 pci_ehci_read_reg(int reg);

extern void pci_ide_write_reg(int reg, u32 value);
extern u32 pci_ide_read_reg(int reg);

extern void pci_acc_write_reg(int reg, u32 value);
extern u32 pci_acc_read_reg(int reg);

extern void pci_ohci_write_reg(int reg, u32 value);
extern u32 pci_ohci_read_reg(int reg);

extern void pci_isa_write_bar(int n, u32 value);
extern u32 pci_isa_read_bar(int n);
extern void pci_isa_write_reg(int reg, u32 value);
extern u32 pci_isa_read_reg(int reg);

extern int __init init_mfgpt_clocksource(void);

#define CS5536_ACC_INTR		9
#define CS5536_IDE_INTR		14
#define CS5536_USB_INTR		11
#define CS5536_MFGPT_INTR	5
#define CS5536_UART1_INTR	4
#define CS5536_UART2_INTR	3

/************** PCI BUS DEVICE FUNCTION ***************/

/*
 * PCI bus device function
 */
#define PCI_BUS_CS5536		0
#define PCI_IDSEL_CS5536	14

/********** STANDARD PCI-2.2 EXPANSION ****************/

/*
 * PCI configuration space
 * we have to virtualize the PCI configure space head, so we should
 * define the necessary IDs and some others.
 */

/* CONFIG of PCI VENDOR ID*/
#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
	(((mod_dev_id) << 16) | (sys_vendor_id))

/* VENDOR ID */
#define CS5536_VENDOR_ID	0x1022

/* DEVICE ID */
#define CS5536_ISA_DEVICE_ID		0x2090
#define CS5536_IDE_DEVICE_ID		0x209a
#define CS5536_ACC_DEVICE_ID		0x2093
#define CS5536_OHCI_DEVICE_ID		0x2094
#define CS5536_EHCI_DEVICE_ID		0x2095

/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
#define CS5536_ISA_CLASS_CODE		0x060100
#define CS5536_IDE_CLASS_CODE		0x010180
#define CS5536_ACC_CLASS_CODE		0x040100
#define CS5536_OHCI_CLASS_CODE		0x0C0310
#define CS5536_EHCI_CLASS_CODE		0x0C0320

/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */

#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer)	\
	((PCI_NONE_BIST << 24) | ((header_type) << 16) \
		| ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);

#define PCI_NONE_BIST			0x00	/* RO not implemented yet. */
#define PCI_BRIDGE_HEADER_TYPE		0x80	/* RO */
#define PCI_NORMAL_HEADER_TYPE		0x00
#define PCI_NORMAL_LATENCY_TIMER	0x00
#define PCI_NORMAL_CACHE_LINE_SIZE	0x08	/* RW */

/* BAR */
#define PCI_BAR0_REG			0x10
#define PCI_BAR1_REG			0x14
#define PCI_BAR2_REG			0x18
#define PCI_BAR3_REG			0x1c

Annotation

Implementation Notes