arch/mips/include/asm/mach-ralink/rt305x.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-ralink/rt305x.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-ralink/rt305x.h
Extension
.h
Size
3008 bytes
Lines
117
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _RT305X_REGS_H_
#define _RT305X_REGS_H_

extern enum ralink_soc_type ralink_soc;

static inline int soc_is_rt3050(void)
{
	return ralink_soc == RT305X_SOC_RT3050;
}

static inline int soc_is_rt3052(void)
{
	return ralink_soc == RT305X_SOC_RT3052;
}

static inline int soc_is_rt305x(void)
{
	return soc_is_rt3050() || soc_is_rt3052();
}

static inline int soc_is_rt3350(void)
{
	return ralink_soc == RT305X_SOC_RT3350;
}

static inline int soc_is_rt3352(void)
{
	return ralink_soc == RT305X_SOC_RT3352;
}

static inline int soc_is_rt5350(void)
{
	return ralink_soc == RT305X_SOC_RT5350;
}

#define IOMEM(x)			((void __iomem *)(KSEG1ADDR(x)))
#define RT305X_SYSC_BASE		IOMEM(0x10000000)

#define SYSC_REG_CHIP_NAME0		0x00
#define SYSC_REG_CHIP_NAME1		0x04
#define SYSC_REG_CHIP_ID		0x0c
#define SYSC_REG_SYSTEM_CONFIG		0x10

#define RT3052_CHIP_NAME0		0x30335452
#define RT3052_CHIP_NAME1		0x20203235

#define RT3350_CHIP_NAME0		0x33335452
#define RT3350_CHIP_NAME1		0x20203035

#define RT3352_CHIP_NAME0		0x33335452
#define RT3352_CHIP_NAME1		0x20203235

#define RT5350_CHIP_NAME0		0x33355452
#define RT5350_CHIP_NAME1		0x20203035

#define CHIP_ID_ID_MASK			0xff
#define CHIP_ID_ID_SHIFT		8
#define CHIP_ID_REV_MASK		0xff

#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT	2
#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT		0x1

#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
#define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
#define RT5350_SYSCFG0_DRAM_SIZE_2M     0
#define RT5350_SYSCFG0_DRAM_SIZE_8M     1
#define RT5350_SYSCFG0_DRAM_SIZE_16M    2
#define RT5350_SYSCFG0_DRAM_SIZE_32M    3
#define RT5350_SYSCFG0_DRAM_SIZE_64M    4

/* multi function gpio pins */
#define RT305X_GPIO_I2C_SD		1
#define RT305X_GPIO_I2C_SCLK		2
#define RT305X_GPIO_SPI_EN		3
#define RT305X_GPIO_SPI_CLK		4
/* GPIO 7-14 is shared between UART0, PCM  and I2S interfaces */
#define RT305X_GPIO_7			7
#define RT305X_GPIO_10			10
#define RT305X_GPIO_14			14
#define RT305X_GPIO_UART1_TXD		15
#define RT305X_GPIO_UART1_RXD		16
#define RT305X_GPIO_JTAG_TDO		17
#define RT305X_GPIO_JTAG_TDI		18
#define RT305X_GPIO_MDIO_MDC		22
#define RT305X_GPIO_MDIO_MDIO		23
#define RT305X_GPIO_SDRAM_MD16		24
#define RT305X_GPIO_SDRAM_MD31		39
#define RT305X_GPIO_GE0_TXD0		40
#define RT305X_GPIO_GE0_RXCLK		51

Annotation

Implementation Notes