arch/mips/include/asm/mach-rc32434/pci.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mach-rc32434/pci.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mach-rc32434/pci.h
Extension
.h
Size
13941 bytes
Lines
479
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pci_map {
	u32 address;		/* Address. */
	u32 control;		/* Control. */
	u32 mapping;		/* mapping. */
};

struct pci_reg {
	u32 pcic;
	u32 pcis;
	u32 pcism;
	u32 pcicfga;
	u32 pcicfgd;
	volatile struct pci_map pcilba[PCI_LBA_COUNT];
	u32 pcidac;
	u32 pcidas;
	u32 pcidasm;
	u32 pcidad;
	u32 pcidma8c;
	u32 pcidma9c;
	u32 pcitc;
};

#define PCI_MSU_COUNT		2

struct pci_msu {
	u32 pciim[PCI_MSU_COUNT];
	u32 pciom[PCI_MSU_COUNT];
	u32 pciid;
	u32 pciiic;
	u32 pciiim;
	u32 pciiod;
	u32 pciioic;
	u32 pciioim;
};

/*
 * PCI Control Register
 */

#define PCI_CTL_EN		(1 << 0)
#define PCI_CTL_TNR		(1 << 1)
#define PCI_CTL_SCE		(1 << 2)
#define PCI_CTL_IEN		(1 << 3)
#define PCI_CTL_AAA		(1 << 4)
#define PCI_CTL_EAP		(1 << 5)
#define PCI_CTL_PCIM_BIT	6
#define PCI_CTL_PCIM		0x000001c0

#define PCI_CTL_PCIM_DIS	0
#define PCI_CTL_PCIM_TNR	1 /* Satellite - target not ready */
#define PCI_CTL_PCIM_SUS	2 /* Satellite - suspended CPU. */
#define PCI_CTL_PCIM_EXT	3 /* Host - external arbiter. */
#define PCI_CTL PCIM_PRIO	4 /* Host - fixed priority arb. */
#define PCI_CTL_PCIM_RR		5 /* Host - round robin priority. */
#define PCI_CTL_PCIM_RSVD6	6
#define PCI_CTL_PCIM_RSVD7	7

#define PCI_CTL_IGM		(1 << 9)

/*
 * PCI Status Register
 */

#define PCI_STAT_EED		(1 << 0)
#define PCI_STAT_WR		(1 << 1)
#define PCI_STAT_NMI		(1 << 2)
#define PCI_STAT_II		(1 << 3)
#define PCI_STAT_CWE		(1 << 4)
#define PCI_STAT_CRE		(1 << 5)
#define PCI_STAT_MDPE		(1 << 6)
#define PCI_STAT_STA		(1 << 7)
#define PCI_STAT_RTA		(1 << 8)
#define PCI_STAT_RMA		(1 << 9)
#define PCI_STAT_SSE		(1 << 10)
#define PCI_STAT_OSE		(1 << 11)
#define PCI_STAT_PE		(1 << 12)
#define PCI_STAT_TAE		(1 << 13)
#define PCI_STAT_RLE		(1 << 14)
#define PCI_STAT_BME		(1 << 15)
#define PCI_STAT_PRD		(1 << 16)
#define PCI_STAT_RIP		(1 << 17)

/*
 * PCI Status Mask Register
 */

#define PCI_STATM_EED		PCI_STAT_EED
#define PCI_STATM_WR		PCI_STAT_WR
#define PCI_STATM_NMI		PCI_STAT_NMI
#define PCI_STATM_II		PCI_STAT_II

Annotation

Implementation Notes