arch/mips/include/asm/mips-boards/msc01_pci.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/mips-boards/msc01_pci.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/mips-boards/msc01_pci.h
Extension
.h
Size
10433 bytes
Lines
259
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
#define __ASM_MIPS_BOARDS_MSC01_PCI_H

/*
 * Register offset addresses
 */

#define MSC01_PCI_ID_OFS		0x0000
#define MSC01_PCI_SC2PMBASL_OFS		0x0208
#define MSC01_PCI_SC2PMMSKL_OFS		0x0218
#define MSC01_PCI_SC2PMMAPL_OFS		0x0228
#define MSC01_PCI_SC2PIOBASL_OFS	0x0248
#define MSC01_PCI_SC2PIOMSKL_OFS	0x0258
#define MSC01_PCI_SC2PIOMAPL_OFS	0x0268
#define MSC01_PCI_P2SCMSKL_OFS		0x0308
#define MSC01_PCI_P2SCMAPL_OFS		0x0318
#define MSC01_PCI_INTCFG_OFS		0x0600
#define MSC01_PCI_INTSTAT_OFS		0x0608
#define MSC01_PCI_CFGADDR_OFS		0x0610
#define MSC01_PCI_CFGDATA_OFS		0x0618
#define MSC01_PCI_IACK_OFS		0x0620
#define MSC01_PCI_HEAD0_OFS		0x2000	/* DevID, VendorID */
#define MSC01_PCI_HEAD1_OFS		0x2008	/* Status, Command */
#define MSC01_PCI_HEAD2_OFS		0x2010	/* Class code, RevID */
#define MSC01_PCI_HEAD3_OFS		0x2018	/* bist, header, latency */
#define MSC01_PCI_HEAD4_OFS		0x2020	/* BAR 0 */
#define MSC01_PCI_HEAD5_OFS		0x2028	/* BAR 1 */
#define MSC01_PCI_HEAD6_OFS		0x2030	/* BAR 2 */
#define MSC01_PCI_HEAD7_OFS		0x2038	/* BAR 3 */
#define MSC01_PCI_HEAD8_OFS		0x2040	/* BAR 4 */
#define MSC01_PCI_HEAD9_OFS		0x2048	/* BAR 5 */
#define MSC01_PCI_HEAD10_OFS		0x2050	/* CardBus CIS Ptr */
#define MSC01_PCI_HEAD11_OFS		0x2058	/* SubSystem ID, -VendorID */
#define MSC01_PCI_HEAD12_OFS		0x2060	/* ROM BAR */
#define MSC01_PCI_HEAD13_OFS		0x2068	/* Capabilities ptr */
#define MSC01_PCI_HEAD14_OFS		0x2070	/* reserved */
#define MSC01_PCI_HEAD15_OFS		0x2078	/* Maxl, ming, intpin, int */
#define MSC01_PCI_BAR0_OFS		0x2220
#define MSC01_PCI_CFG_OFS		0x2380
#define MSC01_PCI_SWAP_OFS		0x2388


/*****************************************************************************
 * Register encodings
 ****************************************************************************/

#define MSC01_PCI_ID_ID_SHF		16
#define MSC01_PCI_ID_ID_MSK		0x00ff0000
#define MSC01_PCI_ID_ID_HOSTBRIDGE	82
#define MSC01_PCI_ID_MAR_SHF		8
#define MSC01_PCI_ID_MAR_MSK		0x0000ff00
#define MSC01_PCI_ID_MIR_SHF		0
#define MSC01_PCI_ID_MIR_MSK		0x000000ff

#define MSC01_PCI_SC2PMBASL_BAS_SHF	24
#define MSC01_PCI_SC2PMBASL_BAS_MSK	0xff000000

#define MSC01_PCI_SC2PMMSKL_MSK_SHF	24
#define MSC01_PCI_SC2PMMSKL_MSK_MSK	0xff000000

#define MSC01_PCI_SC2PMMAPL_MAP_SHF	24
#define MSC01_PCI_SC2PMMAPL_MAP_MSK	0xff000000

#define MSC01_PCI_SC2PIOBASL_BAS_SHF	24
#define MSC01_PCI_SC2PIOBASL_BAS_MSK	0xff000000

#define MSC01_PCI_SC2PIOMSKL_MSK_SHF	24
#define MSC01_PCI_SC2PIOMSKL_MSK_MSK	0xff000000

#define MSC01_PCI_SC2PIOMAPL_MAP_SHF	24
#define MSC01_PCI_SC2PIOMAPL_MAP_MSK	0xff000000

#define MSC01_PCI_P2SCMSKL_MSK_SHF	24
#define MSC01_PCI_P2SCMSKL_MSK_MSK	0xff000000

#define MSC01_PCI_P2SCMAPL_MAP_SHF	24
#define MSC01_PCI_P2SCMAPL_MAP_MSK	0xff000000

#define MSC01_PCI_INTCFG_RST_SHF	10
#define MSC01_PCI_INTCFG_RST_MSK	0x00000400
#define MSC01_PCI_INTCFG_RST_BIT	0x00000400
#define MSC01_PCI_INTCFG_MWE_SHF	9
#define MSC01_PCI_INTCFG_MWE_MSK	0x00000200
#define MSC01_PCI_INTCFG_MWE_BIT	0x00000200
#define MSC01_PCI_INTCFG_DTO_SHF	8
#define MSC01_PCI_INTCFG_DTO_MSK	0x00000100
#define MSC01_PCI_INTCFG_DTO_BIT	0x00000100
#define MSC01_PCI_INTCFG_MA_SHF		7
#define MSC01_PCI_INTCFG_MA_MSK		0x00000080
#define MSC01_PCI_INTCFG_MA_BIT		0x00000080

Annotation

Implementation Notes