arch/mips/include/asm/octeon/cvmx-address.h

Source file repositories/reference/linux-study-clean/arch/mips/include/asm/octeon/cvmx-address.h

File Facts

System
Linux kernel
Corpus path
arch/mips/include/asm/octeon/cvmx-address.h
Extension
.h
Size
9370 bytes
Lines
342
Domain
Architecture Layer
Bucket
arch/mips
Inferred role
Architecture Layer: implementation source
Status
source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __CVMX_ADDRESS_H__
#define __CVMX_ADDRESS_H__

#if 0
typedef enum {
	CVMX_MIPS_SPACE_XKSEG = 3LL,
	CVMX_MIPS_SPACE_XKPHYS = 2LL,
	CVMX_MIPS_SPACE_XSSEG = 1LL,
	CVMX_MIPS_SPACE_XUSEG = 0LL
} cvmx_mips_space_t;
#endif

typedef enum {
	CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
	CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
	CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
	CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
} cvmx_mips_xkseg_space_t;

/* decodes <14:13> of a kseg3 window address */
typedef enum {
	CVMX_ADD_WIN_SCR = 0L,
	/* see cvmx_add_win_dma_dec_t for further decode */
	CVMX_ADD_WIN_DMA = 1L,
	CVMX_ADD_WIN_UNUSED = 2L,
	CVMX_ADD_WIN_UNUSED2 = 3L
} cvmx_add_win_dec_t;

/* decode within DMA space */
typedef enum {
	/*
	 * Add store data to the write buffer entry, allocating it if
	 * necessary.
	 */
	CVMX_ADD_WIN_DMA_ADD = 0L,
	/* send out the write buffer entry to DRAM */
	CVMX_ADD_WIN_DMA_SENDMEM = 1L,
	/* store data must be normal DRAM memory space address in this case */
	/* send out the write buffer entry as an IOBDMA command */
	CVMX_ADD_WIN_DMA_SENDDMA = 2L,
	/* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
	/* send out the write buffer entry as an IO write */
	CVMX_ADD_WIN_DMA_SENDIO = 3L,
	/* store data must be normal IO space address in this case */
	/* send out a single-tick command on the NCB bus */
	CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
	/* no write buffer data needed/used */
} cvmx_add_win_dma_dec_t;

/*
 *   Physical Address Decode
 *
 * Octeon-I HW never interprets this X (<39:36> reserved
 * for future expansion), software should set to 0.
 *
 *  - 0x0 XXX0 0000 0000 to	 DRAM	      Cached
 *  - 0x0 XXX0 0FFF FFFF
 *
 *  - 0x0 XXX0 1000 0000 to	 Boot Bus     Uncached	(Converted to 0x1 00X0 1000 0000
 *  - 0x0 XXX0 1FFF FFFF	 + EJTAG			   to 0x1 00X0 1FFF FFFF)
 *
 *  - 0x0 XXX0 2000 0000 to	 DRAM	      Cached
 *  - 0x0 XXXF FFFF FFFF
 *
 *  - 0x1 00X0 0000 0000 to	 Boot Bus     Uncached
 *  - 0x1 00XF FFFF FFFF
 *
 *  - 0x1 01X0 0000 0000 to	 Other NCB    Uncached
 *  - 0x1 FFXF FFFF FFFF	 devices
 *
 * Decode of all Octeon addresses
 */
typedef union {

	uint64_t u64;
#ifdef __BIG_ENDIAN_BITFIELD
	/* mapped or unmapped virtual address */
	struct {
		uint64_t R:2;
		uint64_t offset:62;
	} sva;

	/* mapped USEG virtual addresses (typically) */
	struct {
		uint64_t zeroes:33;
		uint64_t offset:31;
	} suseg;

	/* mapped or unmapped virtual address */
	struct {

Annotation

Implementation Notes