arch/mips/include/asm/octeon/cvmx-fau.h
Source file repositories/reference/linux-study-clean/arch/mips/include/asm/octeon/cvmx-fau.h
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/include/asm/octeon/cvmx-fau.h- Extension
.h- Size
- 18651 bytes
- Lines
- 620
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
function __cvmx_fau_store_addressfunction __cvmx_fau_atomic_addressfunction cvmx_fau_fetch_and_add64function cvmx_fau_fetch_and_add32function cvmx_fau_fetch_and_add16function cvmx_fau_fetch_and_add8function cvmx_fau_tagwait_fetch_and_add64function cvmx_fau_tagwait_fetch_and_add32function cvmx_fau_tagwait_fetch_and_add16function cvmx_fau_tagwait_fetch_and_add8function __cvmx_fau_iobdma_datafunction cvmx_fau_async_fetch_and_add64function cvmx_fau_async_fetch_and_add32function cvmx_fau_async_fetch_and_add16function cvmx_fau_async_fetch_and_add8function cvmx_fau_async_tagwait_fetch_and_add64function cvmx_fau_async_tagwait_fetch_and_add32function cvmx_fau_async_tagwait_fetch_and_add16function cvmx_fau_async_tagwait_fetch_and_add8function cvmx_fau_atomic_add64function cvmx_fau_atomic_add32function cvmx_fau_atomic_add16function cvmx_fau_atomic_add8function cvmx_fau_atomic_write64function cvmx_fau_atomic_write32function cvmx_fau_atomic_write16function cvmx_fau_atomic_write8
Annotated Snippet
#ifndef __CVMX_FAU_H__
#define __CVMX_FAU_H__
/*
* Octeon Fetch and Add Unit (FAU)
*/
#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0)
#define CVMX_FAU_BITS_SCRADDR 63, 56
#define CVMX_FAU_BITS_LEN 55, 48
#define CVMX_FAU_BITS_INEVAL 35, 14
#define CVMX_FAU_BITS_TAGWAIT 13, 13
#define CVMX_FAU_BITS_NOADD 13, 13
#define CVMX_FAU_BITS_SIZE 12, 11
#define CVMX_FAU_BITS_REGISTER 10, 0
typedef enum {
CVMX_FAU_OP_SIZE_8 = 0,
CVMX_FAU_OP_SIZE_16 = 1,
CVMX_FAU_OP_SIZE_32 = 2,
CVMX_FAU_OP_SIZE_64 = 3
} cvmx_fau_op_size_t;
/**
* Tagwait return definition. If a timeout occurs, the error
* bit will be set. Otherwise the value of the register before
* the update will be returned.
*/
typedef struct {
uint64_t error:1;
int64_t value:63;
} cvmx_fau_tagwait64_t;
/**
* Tagwait return definition. If a timeout occurs, the error
* bit will be set. Otherwise the value of the register before
* the update will be returned.
*/
typedef struct {
uint64_t error:1;
int32_t value:31;
} cvmx_fau_tagwait32_t;
/**
* Tagwait return definition. If a timeout occurs, the error
* bit will be set. Otherwise the value of the register before
* the update will be returned.
*/
typedef struct {
uint64_t error:1;
int16_t value:15;
} cvmx_fau_tagwait16_t;
/**
* Tagwait return definition. If a timeout occurs, the error
* bit will be set. Otherwise the value of the register before
* the update will be returned.
*/
typedef struct {
uint64_t error:1;
int8_t value:7;
} cvmx_fau_tagwait8_t;
/**
* Asynchronous tagwait return definition. If a timeout occurs,
* the error bit will be set. Otherwise the value of the
* register before the update will be returned.
*/
typedef union {
uint64_t u64;
struct {
uint64_t invalid:1;
uint64_t data:63; /* unpredictable if invalid is set */
} s;
} cvmx_fau_async_tagwait_result_t;
#ifdef __BIG_ENDIAN_BITFIELD
#define SWIZZLE_8 0
#define SWIZZLE_16 0
#define SWIZZLE_32 0
#else
#define SWIZZLE_8 0x7
#define SWIZZLE_16 0x6
#define SWIZZLE_32 0x4
#endif
/**
* Builds a store I/O address for writing to the FAU
*
* @noadd: 0 = Store value is atomically added to the current value
Annotation
- Detected declarations: `function __cvmx_fau_store_address`, `function __cvmx_fau_atomic_address`, `function cvmx_fau_fetch_and_add64`, `function cvmx_fau_fetch_and_add32`, `function cvmx_fau_fetch_and_add16`, `function cvmx_fau_fetch_and_add8`, `function cvmx_fau_tagwait_fetch_and_add64`, `function cvmx_fau_tagwait_fetch_and_add32`, `function cvmx_fau_tagwait_fetch_and_add16`, `function cvmx_fau_tagwait_fetch_and_add8`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.