arch/mips/include/asm/octeon/cvmx-npei-defs.h

File Facts

System

Linux kernel

Corpus path

arch/mips/include/asm/octeon/cvmx-npei-defs.h

Extension

.h

Size

84985 bytes

Lines

3926

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct cvmx_npei_bar1_indexx_s
• struct cvmx_npei_bist_status_s
• struct cvmx_npei_bist_status_cn52xx
• struct cvmx_npei_bist_status_cn52xxp1
• struct cvmx_npei_bist_status_cn56xxp1
• struct cvmx_npei_bist_status2_s
• struct cvmx_npei_ctl_port0_s
• struct cvmx_npei_ctl_port1_s
• struct cvmx_npei_ctl_status_s
• struct cvmx_npei_ctl_status_cn52xxp1
• struct cvmx_npei_ctl_status_cn56xxp1
• struct cvmx_npei_ctl_status2_s
• struct cvmx_npei_data_out_cnt_s
• struct cvmx_npei_dbg_data_s
• struct cvmx_npei_dbg_data_cn52xx
• struct cvmx_npei_dbg_data_cn56xx
• struct cvmx_npei_dbg_select_s
• struct cvmx_npei_dmax_counts_s
• struct cvmx_npei_dmax_dbell_s
• struct cvmx_npei_dmax_ibuff_saddr_s
• struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1
• struct cvmx_npei_dmax_naddr_s
• struct cvmx_npei_dma0_int_level_s
• struct cvmx_npei_dma1_int_level_s
• struct cvmx_npei_dma_cnts_s
• struct cvmx_npei_dma_control_s
• struct cvmx_npei_dma_control_cn52xxp1
• struct cvmx_npei_dma_control_cn56xxp1
• struct cvmx_npei_dma_pcie_req_num_s
• struct cvmx_npei_dma_state1_s
• struct cvmx_npei_dma_state1_p1_s
• struct cvmx_npei_dma_state1_p1_cn52xxp1
• struct cvmx_npei_dma_state2_s
• struct cvmx_npei_dma_state2_p1_s
• struct cvmx_npei_dma_state2_p1_cn52xxp1
• struct cvmx_npei_dma_state3_p1_s
• struct cvmx_npei_dma_state4_p1_s
• struct cvmx_npei_dma_state5_p1_s
• struct cvmx_npei_int_a_enb_s
• struct cvmx_npei_int_a_enb_cn52xxp1
• struct cvmx_npei_int_a_enb2_s
• struct cvmx_npei_int_a_enb2_cn52xxp1
• struct cvmx_npei_int_a_sum_s
• struct cvmx_npei_int_a_sum_cn52xxp1
• struct cvmx_npei_int_enb_s
• struct cvmx_npei_int_enb_cn52xxp1
• struct cvmx_npei_int_enb_cn56xxp1
• struct cvmx_npei_int_enb2_s

Annotated Snippet

struct cvmx_npei_bar1_indexx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint32_t reserved_18_31:14;
		uint32_t addr_idx:14;
		uint32_t ca:1;
		uint32_t end_swp:2;
		uint32_t addr_v:1;
#else
		uint32_t addr_v:1;
		uint32_t end_swp:2;
		uint32_t ca:1;
		uint32_t addr_idx:14;
		uint32_t reserved_18_31:14;
#endif
	} s;
};

union cvmx_npei_bist_status {
	uint64_t u64;
	struct cvmx_npei_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t pkt_rdf:1;
		uint64_t reserved_60_62:3;
		uint64_t pcr_gim:1;
		uint64_t pkt_pif:1;
		uint64_t pcsr_int:1;
		uint64_t pcsr_im:1;
		uint64_t pcsr_cnt:1;
		uint64_t pcsr_id:1;
		uint64_t pcsr_sl:1;
		uint64_t reserved_50_52:3;
		uint64_t pkt_ind:1;
		uint64_t pkt_slm:1;
		uint64_t reserved_36_47:12;
		uint64_t d0_pst:1;
		uint64_t d1_pst:1;
		uint64_t d2_pst:1;
		uint64_t d3_pst:1;
		uint64_t reserved_31_31:1;
		uint64_t n2p0_c:1;
		uint64_t n2p0_o:1;
		uint64_t n2p1_c:1;
		uint64_t n2p1_o:1;
		uint64_t cpl_p0:1;
		uint64_t cpl_p1:1;
		uint64_t p2n1_po:1;
		uint64_t p2n1_no:1;
		uint64_t p2n1_co:1;
		uint64_t p2n0_po:1;
		uint64_t p2n0_no:1;
		uint64_t p2n0_co:1;
		uint64_t p2n0_c0:1;
		uint64_t p2n0_c1:1;
		uint64_t p2n0_n:1;
		uint64_t p2n0_p0:1;
		uint64_t p2n0_p1:1;
		uint64_t p2n1_c0:1;
		uint64_t p2n1_c1:1;
		uint64_t p2n1_n:1;
		uint64_t p2n1_p0:1;
		uint64_t p2n1_p1:1;
		uint64_t csm0:1;
		uint64_t csm1:1;
		uint64_t dif0:1;
		uint64_t dif1:1;
		uint64_t dif2:1;
		uint64_t dif3:1;
		uint64_t reserved_2_2:1;
		uint64_t msi:1;
		uint64_t ncb_cmd:1;
#else
		uint64_t ncb_cmd:1;
		uint64_t msi:1;
		uint64_t reserved_2_2:1;
		uint64_t dif3:1;
		uint64_t dif2:1;
		uint64_t dif1:1;
		uint64_t dif0:1;
		uint64_t csm1:1;
		uint64_t csm0:1;
		uint64_t p2n1_p1:1;
		uint64_t p2n1_p0:1;
		uint64_t p2n1_n:1;
		uint64_t p2n1_c1:1;
		uint64_t p2n1_c0:1;
		uint64_t p2n0_p1:1;
		uint64_t p2n0_p0:1;
		uint64_t p2n0_n:1;
		uint64_t p2n0_c1:1;
		uint64_t p2n0_c0:1;

Annotation

• Detected declarations: `struct cvmx_npei_bar1_indexx_s`, `struct cvmx_npei_bist_status_s`, `struct cvmx_npei_bist_status_cn52xx`, `struct cvmx_npei_bist_status_cn52xxp1`, `struct cvmx_npei_bist_status_cn56xxp1`, `struct cvmx_npei_bist_status2_s`, `struct cvmx_npei_ctl_port0_s`, `struct cvmx_npei_ctl_port1_s`, `struct cvmx_npei_ctl_status_s`, `struct cvmx_npei_ctl_status_cn52xxp1`.
• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.