arch/mips/include/asm/octeon/cvmx-npi-defs.h

File Facts

System

Linux kernel

Corpus path

arch/mips/include/asm/octeon/cvmx-npi-defs.h

Extension

.h

Size

59612 bytes

Lines

2515

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct cvmx_npi_base_addr_inputx_s
• struct cvmx_npi_base_addr_outputx_s
• struct cvmx_npi_bist_status_s
• struct cvmx_npi_bist_status_cn30xx
• struct cvmx_npi_bist_status_cn50xx
• struct cvmx_npi_buff_size_outputx_s
• struct cvmx_npi_comp_ctl_s
• struct cvmx_npi_ctl_status_s
• struct cvmx_npi_ctl_status_cn30xx
• struct cvmx_npi_ctl_status_cn31xx
• struct cvmx_npi_dbg_select_s
• struct cvmx_npi_dma_control_s
• struct cvmx_npi_dma_highp_counts_s
• struct cvmx_npi_dma_highp_naddr_s
• struct cvmx_npi_dma_lowp_counts_s
• struct cvmx_npi_dma_lowp_naddr_s
• struct cvmx_npi_highp_dbell_s
• struct cvmx_npi_highp_ibuff_saddr_s
• struct cvmx_npi_input_control_s
• struct cvmx_npi_input_control_cn30xx
• struct cvmx_npi_int_enb_s
• struct cvmx_npi_int_enb_cn30xx
• struct cvmx_npi_int_enb_cn31xx
• struct cvmx_npi_int_enb_cn38xxp2
• struct cvmx_npi_int_sum_s
• struct cvmx_npi_int_sum_cn30xx
• struct cvmx_npi_int_sum_cn31xx
• struct cvmx_npi_int_sum_cn38xxp2
• struct cvmx_npi_lowp_dbell_s
• struct cvmx_npi_lowp_ibuff_saddr_s
• struct cvmx_npi_mem_access_subidx_s
• struct cvmx_npi_mem_access_subidx_cn31xx
• struct cvmx_npi_msi_rcv_s
• struct cvmx_npi_num_desc_outputx_s
• struct cvmx_npi_output_control_s
• struct cvmx_npi_output_control_cn30xx
• struct cvmx_npi_output_control_cn31xx
• struct cvmx_npi_output_control_cn38xxp2
• struct cvmx_npi_output_control_cn50xx
• struct cvmx_npi_px_dbpair_addr_s
• struct cvmx_npi_px_instr_addr_s
• struct cvmx_npi_px_instr_cnts_s
• struct cvmx_npi_px_pair_cnts_s
• struct cvmx_npi_pci_burst_size_s
• struct cvmx_npi_pci_int_arb_cfg_s
• struct cvmx_npi_pci_int_arb_cfg_cn30xx
• struct cvmx_npi_pci_read_cmd_s
• struct cvmx_npi_port32_instr_hdr_s

Annotated Snippet

struct cvmx_npi_base_addr_inputx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t baddr:61;
		uint64_t reserved_0_2:3;
#else
		uint64_t reserved_0_2:3;
		uint64_t baddr:61;
#endif
	} s;
};

union cvmx_npi_base_addr_outputx {
	uint64_t u64;
	struct cvmx_npi_base_addr_outputx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t baddr:61;
		uint64_t reserved_0_2:3;
#else
		uint64_t reserved_0_2:3;
		uint64_t baddr:61;
#endif
	} s;
};

union cvmx_npi_bist_status {
	uint64_t u64;
	struct cvmx_npi_bist_status_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_20_63:44;
		uint64_t csr_bs:1;
		uint64_t dif_bs:1;
		uint64_t rdp_bs:1;
		uint64_t pcnc_bs:1;
		uint64_t pcn_bs:1;
		uint64_t rdn_bs:1;
		uint64_t pcac_bs:1;
		uint64_t pcad_bs:1;
		uint64_t rdnl_bs:1;
		uint64_t pgf_bs:1;
		uint64_t pig_bs:1;
		uint64_t pof0_bs:1;
		uint64_t pof1_bs:1;
		uint64_t pof2_bs:1;
		uint64_t pof3_bs:1;
		uint64_t pos_bs:1;
		uint64_t nus_bs:1;
		uint64_t dob_bs:1;
		uint64_t pdf_bs:1;
		uint64_t dpi_bs:1;
#else
		uint64_t dpi_bs:1;
		uint64_t pdf_bs:1;
		uint64_t dob_bs:1;
		uint64_t nus_bs:1;
		uint64_t pos_bs:1;
		uint64_t pof3_bs:1;
		uint64_t pof2_bs:1;
		uint64_t pof1_bs:1;
		uint64_t pof0_bs:1;
		uint64_t pig_bs:1;
		uint64_t pgf_bs:1;
		uint64_t rdnl_bs:1;
		uint64_t pcad_bs:1;
		uint64_t pcac_bs:1;
		uint64_t rdn_bs:1;
		uint64_t pcn_bs:1;
		uint64_t pcnc_bs:1;
		uint64_t rdp_bs:1;
		uint64_t dif_bs:1;
		uint64_t csr_bs:1;
		uint64_t reserved_20_63:44;
#endif
	} s;
	struct cvmx_npi_bist_status_cn30xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_20_63:44;
		uint64_t csr_bs:1;
		uint64_t dif_bs:1;
		uint64_t rdp_bs:1;
		uint64_t pcnc_bs:1;
		uint64_t pcn_bs:1;
		uint64_t rdn_bs:1;
		uint64_t pcac_bs:1;
		uint64_t pcad_bs:1;
		uint64_t rdnl_bs:1;
		uint64_t pgf_bs:1;
		uint64_t pig_bs:1;
		uint64_t pof0_bs:1;
		uint64_t reserved_5_7:3;
		uint64_t pos_bs:1;

Annotation

• Detected declarations: `struct cvmx_npi_base_addr_inputx_s`, `struct cvmx_npi_base_addr_outputx_s`, `struct cvmx_npi_bist_status_s`, `struct cvmx_npi_bist_status_cn30xx`, `struct cvmx_npi_bist_status_cn50xx`, `struct cvmx_npi_buff_size_outputx_s`, `struct cvmx_npi_comp_ctl_s`, `struct cvmx_npi_ctl_status_s`, `struct cvmx_npi_ctl_status_cn30xx`, `struct cvmx_npi_ctl_status_cn31xx`.
• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.