arch/mips/include/asm/octeon/cvmx-pci-defs.h

File Facts

System

Linux kernel

Corpus path

arch/mips/include/asm/octeon/cvmx-pci-defs.h

Extension

.h

Size

43270 bytes

Lines

2038

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct cvmx_pci_bar1_indexx_s
• struct cvmx_pci_bist_reg_s
• struct cvmx_pci_cfg00_s
• struct cvmx_pci_cfg01_s
• struct cvmx_pci_cfg02_s
• struct cvmx_pci_cfg03_s
• struct cvmx_pci_cfg04_s
• struct cvmx_pci_cfg05_s
• struct cvmx_pci_cfg06_s
• struct cvmx_pci_cfg07_s
• struct cvmx_pci_cfg08_s
• struct cvmx_pci_cfg09_s
• struct cvmx_pci_cfg10_s
• struct cvmx_pci_cfg11_s
• struct cvmx_pci_cfg12_s
• struct cvmx_pci_cfg13_s
• struct cvmx_pci_cfg15_s
• struct cvmx_pci_cfg16_s
• struct cvmx_pci_cfg17_s
• struct cvmx_pci_cfg18_s
• struct cvmx_pci_cfg19_s
• struct cvmx_pci_cfg20_s
• struct cvmx_pci_cfg21_s
• struct cvmx_pci_cfg22_s
• struct cvmx_pci_cfg56_s
• struct cvmx_pci_cfg57_s
• struct cvmx_pci_cfg58_s
• struct cvmx_pci_cfg59_s
• struct cvmx_pci_cfg60_s
• struct cvmx_pci_cfg61_s
• struct cvmx_pci_cfg62_s
• struct cvmx_pci_cfg63_s
• struct cvmx_pci_cnt_reg_s
• struct cvmx_pci_ctl_status_2_s
• struct cvmx_pci_ctl_status_2_cn31xx
• struct cvmx_pci_dbellx_s
• struct cvmx_pci_dma_cntx_s
• struct cvmx_pci_dma_int_levx_s
• struct cvmx_pci_dma_timex_s
• struct cvmx_pci_instr_countx_s
• struct cvmx_pci_int_enb_s
• struct cvmx_pci_int_enb_cn30xx
• struct cvmx_pci_int_enb_cn31xx
• struct cvmx_pci_int_enb2_s
• struct cvmx_pci_int_enb2_cn30xx
• struct cvmx_pci_int_enb2_cn31xx
• struct cvmx_pci_int_sum_s
• struct cvmx_pci_int_sum_cn30xx

Annotated Snippet

struct cvmx_pci_bar1_indexx_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint32_t reserved_18_31:14;
		uint32_t addr_idx:14;
		uint32_t ca:1;
		uint32_t end_swp:2;
		uint32_t addr_v:1;
#else
		uint32_t addr_v:1;
		uint32_t end_swp:2;
		uint32_t ca:1;
		uint32_t addr_idx:14;
		uint32_t reserved_18_31:14;
#endif
	} s;
};

union cvmx_pci_bist_reg {
	uint64_t u64;
	struct cvmx_pci_bist_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_10_63:54;
		uint64_t rsp_bs:1;
		uint64_t dma0_bs:1;
		uint64_t cmd0_bs:1;
		uint64_t cmd_bs:1;
		uint64_t csr2p_bs:1;
		uint64_t csrr_bs:1;
		uint64_t rsp2p_bs:1;
		uint64_t csr2n_bs:1;
		uint64_t dat2n_bs:1;
		uint64_t dbg2n_bs:1;
#else
		uint64_t dbg2n_bs:1;
		uint64_t dat2n_bs:1;
		uint64_t csr2n_bs:1;
		uint64_t rsp2p_bs:1;
		uint64_t csrr_bs:1;
		uint64_t csr2p_bs:1;
		uint64_t cmd_bs:1;
		uint64_t cmd0_bs:1;
		uint64_t dma0_bs:1;
		uint64_t rsp_bs:1;
		uint64_t reserved_10_63:54;
#endif
	} s;
};

union cvmx_pci_cfg00 {
	uint32_t u32;
	struct cvmx_pci_cfg00_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint32_t devid:16;
		uint32_t vendid:16;
#else
		uint32_t vendid:16;
		uint32_t devid:16;
#endif
	} s;
};

union cvmx_pci_cfg01 {
	uint32_t u32;
	struct cvmx_pci_cfg01_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint32_t dpe:1;
		uint32_t sse:1;
		uint32_t rma:1;
		uint32_t rta:1;
		uint32_t sta:1;
		uint32_t devt:2;
		uint32_t mdpe:1;
		uint32_t fbb:1;
		uint32_t reserved_22_22:1;
		uint32_t m66:1;
		uint32_t cle:1;
		uint32_t i_stat:1;
		uint32_t reserved_11_18:8;
		uint32_t i_dis:1;
		uint32_t fbbe:1;
		uint32_t see:1;
		uint32_t ads:1;
		uint32_t pee:1;
		uint32_t vps:1;
		uint32_t mwice:1;
		uint32_t scse:1;
		uint32_t me:1;
		uint32_t msae:1;
		uint32_t isae:1;
#else

Annotation

• Detected declarations: `struct cvmx_pci_bar1_indexx_s`, `struct cvmx_pci_bist_reg_s`, `struct cvmx_pci_cfg00_s`, `struct cvmx_pci_cfg01_s`, `struct cvmx_pci_cfg02_s`, `struct cvmx_pci_cfg03_s`, `struct cvmx_pci_cfg04_s`, `struct cvmx_pci_cfg05_s`, `struct cvmx_pci_cfg06_s`, `struct cvmx_pci_cfg07_s`.
• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.