arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h

File Facts

System

Linux kernel

Corpus path

arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h

Extension

.h

Size

19404 bytes

Lines

665

Domain

Architecture Layer

Bucket

arch/mips

Inferred role

Architecture Layer: implementation source

Status

source implementation candidate

Why This File Exists

CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.

• CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct cvmx_pcsxx_10gbx_status_reg_s
• struct cvmx_pcsxx_bist_status_reg_s
• struct cvmx_pcsxx_bit_lock_status_reg_s
• struct cvmx_pcsxx_control1_reg_s
• struct cvmx_pcsxx_control2_reg_s
• struct cvmx_pcsxx_int_en_reg_s
• struct cvmx_pcsxx_int_en_reg_cn52xx
• struct cvmx_pcsxx_int_reg_s
• struct cvmx_pcsxx_int_reg_cn52xx
• struct cvmx_pcsxx_log_anl_reg_s
• struct cvmx_pcsxx_misc_ctl_reg_s
• struct cvmx_pcsxx_rx_sync_states_reg_s
• struct cvmx_pcsxx_spd_abil_reg_s
• struct cvmx_pcsxx_status1_reg_s
• struct cvmx_pcsxx_status2_reg_s
• struct cvmx_pcsxx_tx_rx_polarity_reg_s
• struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1
• struct cvmx_pcsxx_tx_rx_states_reg_s
• struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1
• function CVMX_PCSXX_10GBX_STATUS_REG
• function CVMX_PCSXX_BIST_STATUS_REG
• function CVMX_PCSXX_BIT_LOCK_STATUS_REG
• function CVMX_PCSXX_CONTROL1_REG
• function CVMX_PCSXX_CONTROL2_REG
• function CVMX_PCSXX_INT_EN_REG
• function CVMX_PCSXX_INT_REG
• function CVMX_PCSXX_LOG_ANL_REG
• function CVMX_PCSXX_MISC_CTL_REG
• function CVMX_PCSXX_RX_SYNC_STATES_REG
• function CVMX_PCSXX_SPD_ABIL_REG
• function CVMX_PCSXX_STATUS1_REG
• function CVMX_PCSXX_STATUS2_REG
• function CVMX_PCSXX_TX_RX_POLARITY_REG
• function CVMX_PCSXX_TX_RX_STATES_REG

Annotated Snippet

struct cvmx_pcsxx_10gbx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t alignd:1;
		uint64_t pattst:1;
		uint64_t reserved_4_10:7;
		uint64_t l3sync:1;
		uint64_t l2sync:1;
		uint64_t l1sync:1;
		uint64_t l0sync:1;
#else
		uint64_t l0sync:1;
		uint64_t l1sync:1;
		uint64_t l2sync:1;
		uint64_t l3sync:1;
		uint64_t reserved_4_10:7;
		uint64_t pattst:1;
		uint64_t alignd:1;
		uint64_t reserved_13_63:51;
#endif
	} s;
};

union cvmx_pcsxx_bist_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_bist_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_1_63:63;
		uint64_t bist_status:1;
#else
		uint64_t bist_status:1;
		uint64_t reserved_1_63:63;
#endif
	} s;
};

union cvmx_pcsxx_bit_lock_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_bit_lock_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_4_63:60;
		uint64_t bitlck3:1;
		uint64_t bitlck2:1;
		uint64_t bitlck1:1;
		uint64_t bitlck0:1;
#else
		uint64_t bitlck0:1;
		uint64_t bitlck1:1;
		uint64_t bitlck2:1;
		uint64_t bitlck3:1;
		uint64_t reserved_4_63:60;
#endif
	} s;
};

union cvmx_pcsxx_control1_reg {
	uint64_t u64;
	struct cvmx_pcsxx_control1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t reset:1;
		uint64_t loopbck1:1;
		uint64_t spdsel1:1;
		uint64_t reserved_12_12:1;
		uint64_t lo_pwr:1;
		uint64_t reserved_7_10:4;
		uint64_t spdsel0:1;
		uint64_t spd:4;
		uint64_t reserved_0_1:2;
#else
		uint64_t reserved_0_1:2;
		uint64_t spd:4;
		uint64_t spdsel0:1;
		uint64_t reserved_7_10:4;
		uint64_t lo_pwr:1;
		uint64_t reserved_12_12:1;
		uint64_t spdsel1:1;
		uint64_t loopbck1:1;
		uint64_t reset:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
};

union cvmx_pcsxx_control2_reg {
	uint64_t u64;
	struct cvmx_pcsxx_control2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_2_63:62;
		uint64_t type:2;

Annotation

• Detected declarations: `struct cvmx_pcsxx_10gbx_status_reg_s`, `struct cvmx_pcsxx_bist_status_reg_s`, `struct cvmx_pcsxx_bit_lock_status_reg_s`, `struct cvmx_pcsxx_control1_reg_s`, `struct cvmx_pcsxx_control2_reg_s`, `struct cvmx_pcsxx_int_en_reg_s`, `struct cvmx_pcsxx_int_en_reg_cn52xx`, `struct cvmx_pcsxx_int_reg_s`, `struct cvmx_pcsxx_int_reg_cn52xx`, `struct cvmx_pcsxx_log_anl_reg_s`.
• Atlas domain: Architecture Layer / arch/mips.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.