arch/mips/include/asm/prefetch.h
Source file repositories/reference/linux-study-clean/arch/mips/include/asm/prefetch.h
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/include/asm/prefetch.h- Extension
.h- Size
- 2149 bytes
- Lines
- 88
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __ASM_PREFETCH_H
#define __ASM_PREFETCH_H
/*
* R5000 and RM5200 implements pref and prefx instructions but they're nops, so
* rather than wasting time we pretend these processors don't support
* prefetching at all.
*
* R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
* StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
*
* Hell (and the book on my shelf I can't open ...) know what the R8000 does.
*
* RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
* Pref_PrepareForStore also.
*
* RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
* current versions due to erratum G105.
*
* VR5500 (including VR5701 and VR7701) only implement load prefetch.
*
* Finally MIPS32 and MIPS64 implement all of the following hints.
*/
#define Pref_Load 0
#define Pref_Store 1
/* 2 and 3 are reserved */
#define Pref_LoadStreamed 4
#define Pref_StoreStreamed 5
#define Pref_LoadRetained 6
#define Pref_StoreRetained 7
/* 8 ... 24 are reserved */
#define Pref_WriteBackInvalidate 25
#define Pref_PrepareForStore 30
#ifdef __ASSEMBLER__
.macro __pref hint addr
#ifdef CONFIG_CPU_HAS_PREFETCH
pref \hint, \addr
#endif
.endm
.macro pref_load addr
__pref Pref_Load, \addr
.endm
.macro pref_store addr
__pref Pref_Store, \addr
.endm
.macro pref_load_streamed addr
__pref Pref_LoadStreamed, \addr
.endm
.macro pref_store_streamed addr
__pref Pref_StoreStreamed, \addr
.endm
.macro pref_load_retained addr
__pref Pref_LoadRetained, \addr
.endm
.macro pref_store_retained addr
__pref Pref_StoreRetained, \addr
.endm
.macro pref_wback_inv addr
__pref Pref_WriteBackInvalidate, \addr
.endm
.macro pref_prepare_for_store addr
__pref Pref_PrepareForStore, \addr
.endm
#endif
#endif /* __ASM_PREFETCH_H */
Annotation
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.