arch/mips/include/asm/regdef.h
Source file repositories/reference/linux-study-clean/arch/mips/include/asm/regdef.h
File Facts
- System
- Linux kernel
- Corpus path
arch/mips/include/asm/regdef.h- Extension
.h- Size
- 5069 bytes
- Lines
- 198
- Domain
- Architecture Layer
- Bucket
- arch/mips
- Inferred role
- Architecture Layer: implementation source
- Status
- source implementation candidate
Why This File Exists
CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
- CPU and platform-specific kernel glue: boot entry, traps, syscall entry, interrupts, page tables, context switch, and low-level barriers.
Dependency Surface
asm/sgidefs.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _ASM_REGDEF_H
#define _ASM_REGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
* General purpose register numbers for 32 bit ABI
*/
#define GPR_ZERO 0 /* wired zero */
#define GPR_AT 1 /* assembler temp */
#define GPR_V0 2 /* return value */
#define GPR_V1 3
#define GPR_A0 4 /* argument registers */
#define GPR_A1 5
#define GPR_A2 6
#define GPR_A3 7
#define GPR_T0 8 /* caller saved */
#define GPR_T1 9
#define GPR_T2 10
#define GPR_T3 11
#define GPR_T4 12
#define GPR_TA0 12
#define GPR_T5 13
#define GPR_TA1 13
#define GPR_T6 14
#define GPR_TA2 14
#define GPR_T7 15
#define GPR_TA3 15
#define GPR_S0 16 /* callee saved */
#define GPR_S1 17
#define GPR_S2 18
#define GPR_S3 19
#define GPR_S4 20
#define GPR_S5 21
#define GPR_S6 22
#define GPR_S7 23
#define GPR_T8 24 /* caller saved */
#define GPR_T9 25
#define GPR_JP 25 /* PIC jump register */
#define GPR_K0 26 /* kernel scratch */
#define GPR_K1 27
#define GPR_GP 28 /* global pointer */
#define GPR_SP 29 /* stack pointer */
#define GPR_FP 30 /* frame pointer */
#define GPR_S8 30 /* same like fp! */
#define GPR_RA 31 /* return address */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define GPR_ZERO 0 /* wired zero */
#define GPR_AT 1 /* assembler temp */
#define GPR_V0 2 /* return value - caller saved */
#define GPR_V1 3
#define GPR_A0 4 /* argument registers */
#define GPR_A1 5
#define GPR_A2 6
#define GPR_A3 7
#define GPR_A4 8 /* arg reg 64 bit; caller saved in 32 bit */
#define GPR_TA0 8
#define GPR_A5 9
#define GPR_TA1 9
#define GPR_A6 10
#define GPR_TA2 10
#define GPR_A7 11
#define GPR_TA3 11
#define GPR_T0 12 /* caller saved */
#define GPR_T1 13
#define GPR_T2 14
#define GPR_T3 15
#define GPR_S0 16 /* callee saved */
#define GPR_S1 17
#define GPR_S2 18
#define GPR_S3 19
#define GPR_S4 20
#define GPR_S5 21
#define GPR_S6 22
#define GPR_S7 23
#define GPR_T8 24 /* caller saved */
#define GPR_T9 25 /* callee address for PIC/temp */
#define GPR_JP 25 /* PIC jump register */
#define GPR_K0 26 /* kernel temporary */
#define GPR_K1 27
#define GPR_GP 28 /* global pointer - caller saved for PIC */
#define GPR_SP 29 /* stack pointer */
#define GPR_FP 30 /* frame pointer */
#define GPR_S8 30 /* callee saved */
Annotation
- Immediate include surface: `asm/sgidefs.h`.
- Atlas domain: Architecture Layer / arch/mips.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.